DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 168

• Manufacturer Part Number: DF2398TE20
• Description: IC H8S MCU FLASH 256K 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2398TE20; HD64F2398TE20

6.5
6.5.1
When the H8S/2357 Group is in advanced mode, external space areas 2 to 5 can be designated as DRAM space, and
DRAM interfacing performed. With the DRAM interface, DRAM can be directly connected to the H8S/2357 Group. A
DRAM space of 2, 4, or 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in BCRH. Burst operation is also
possible, using fast page mode.
6.5.2
Areas 2 to 5 are designated as DRAM space by setting bits RMTS2 to RMTS0 in BCRH. The relation between the
settings of bits RMTS2 to RMTS0 and DRAM space is shown in table 6-5. Possible DRAM space settings are: one area
(area 2), two areas (areas 2 and 3), and four areas (areas 2 to 5).
Table 6-5
6.5.3
With DRAM space, the row address and column address are multiplexed. In address multiplexing, the size of the shift of
the row address is selected with bits MXC1 and MXC0 in MCR. Table 6-6 shows the relation between the settings of
MXC1 and MXC0 and the shift size.
Table 6-6
6.5.4
If the bit in ABWCR corresponding to an area designated as DRAM space is set to 1, that area is designated as 8-bit
DRAM space; if the bit is cleared to 0, the area is designated as 16-bit DRAM space. In 16-bit DRAM space, 16-bit
configuration DRAM can be connected directly.
In 8-bit DRAM space the upper half of the data bus, D
lower halves of the data bus, D
Access sizes and data alignment are the same as for the basic bus interface: see section 6.4.2, Data Size and Data
Alignment.
Rev.6.00 Oct.28.2004 page 138 of 1016
REJ09B0138-0600H
DRAM Interface
Overview
Setting DRAM Space
Address Multiplexing
Data Bus
RMTS2
0
Row
address
Column
address
Settings of Bits RMTS2 to RMTS0 and Corresponding DRAM Spaces
Address Multiplexing Settings by Bits MXC1 and MXC0
MXC1 MXC0 Size
0
1
—
RMTS1
0
1
MCR
0
1
0
1
—
15
to D
Shift
8 bits
9 bits
10 bits
Setting
prohibited
—
RMTS0
1
0
1
0
, are enabled.
A
A
A
A
—
A
23
23
23
23
23
Area 5
Normal space
Normal space
DRAM space
to A
to A
to A
to A
to A
13
13
13
13
13
15
A
A
A
A
— — — — — — — — — — — — —
A
to D
12
20
12
12
12
A
A
A
A
A
8
11
19
20
11
11
, is enabled, while in 16-bit DRAM space both the upper and
A
A
A
A
A
10
18
19
20
10
Area 4
A
A
A
A
A
9
17
18
19
9
Address Pins
A
A
A
A
A
8
16
17
18
8
A
A
A
A
A
7
15
16
17
7
Area 3
DRAM space
A
A
A
A
A
6
14
15
16
6
A
A
A
A
A
5
13
14
15
5
A
A
A
A
A
4
12
13
14
4
A
A
A
A
A
3
11
12
13
3
Area 2
DRAM space
A
A
A
A
A
2
10
11
12
2
A
A
A
A
A
1
9
10
11
1
A
A
A
A
A
0
8
9
10
0