DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 79

• Manufacturer Part Number: DF2398TE20
• Description: IC H8S MCU FLASH 256K 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2398TE20; HD64F2398TE20

Table 2-7
Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception-handling is not executed at the end of the
(2) Reset Exception Handling
After the RES pin has gone low and the reset state has been entered, when RES goes high again, reset exception handling
starts. The CPU enters the power-on reset state when the NMI pin is high, or the manual reset* state when the NMI pin is
low. When reset exception handling starts the CPU fetches a start address (vector) from the exception vector table and
starts program execution from that address. All interrupts, including NMI, are disabled during reset exception handling
and after it ends.
Note : * Manual reset is only supported in the H8S/2357 ZTAT.
(3) Traces
Traces are enabled only in interrupt control mode 2. Trace mode is entered when the T bit of EXR is set to 1. When trace
mode is established, trace exception handling starts at the end of each instruction.
At the end of a trace exception-handling sequence, the T bit of EXR is cleared to 0 and trace mode is cleared. Interrupt
masks are not affected.
The T bit saved on the stack retains its value of 1, and when the RTE instruction is executed to return from the trace
exception-handling routine, trace mode is entered again. Trace exception-handling is not executed at the end of the RTE
instruction.
Trace mode is not entered in interrupt control mode 0, regardless of the state of the T bit.
(4) Interrupt Exception Handling and Trap Instruction Exception Handling
When interrupt or trap-instruction exception handling begins, the CPU references the stack pointer (ER7) and pushes the
program counter and other control registers onto the stack. Next, the CPU alters the settings of the interrupt mask bits in
the control registers. Then the CPU fetches a start address (vector) from the exception vector table and program execution
starts from that start address.
2. Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions, or immediately after
3. Trap instruction exception handling is always accepted, in the program execution state.
RTE instruction.
reset exception handling.
Priority
High
Low
Exception Handling Types and Priority
Type of Exception
Reset
Trace
Interrupt
Trap instruction
Detection Timing
Synchronized with clock
End of instruction
execution or end of
exception-handling
sequence*
End of instruction
execution or end of
exception-handling
sequence*
When TRAPA instruction
is executed
1
2
Start of Exception Handling
Exception handling starts
immediately after a low-to-high
transition at the RES pin, or
when the watchdog timer
overflows.
When the trace (T) bit is set to
1, the trace starts at the end of
the current instruction or current
exception-handling sequence
When an interrupt is requested,
exception handling starts at the
end of the current instruction or
current exception-handling
sequence
Exception handling starts when
a trap (TRAPA) instruction is
executed*
Rev.6.00 Oct.28.2004 page 49 of 1016
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