DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 473

IC H8S MCU FLASH 256K 120TQFP

DF2398TE20

Manufacturer Part Number
DF2398TE20
Description
IC H8S MCU FLASH 256K 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets

Specifications of DF2398TE20

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2398TE20
HD64F2398TE20

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2398TE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
12.3.2
Setting of Compare Match Flags A and B (CMFA, CMFB): The CMFA and CMFB flags in TCSR are set to 1 by a
compare match signal generated when the TCOR and TCNT values match. The compare match signal is generated at the
last state in which the match is true, just before the timer counter is updated.
Therefore, when TCOR and TCNT match, the compare match signal is not generated until the next incrementation clock
input. Figure 12-4 shows this timing.
Timer Output Timing: When compare match A or B occurs, the timer output changes a specified by bits OS3 to OS0 in
TCSR. Depending on these bits, the output can remain the same, change to 0, change to 1, or toggle.
Figure 12-5 shows the timing when the output is set to toggle at compare match A.
Timing of Compare Match Clear: The timer counter is cleared when compare match A or B occurs, depending on the
setting of the CCLR1 and CCLR0 bits in TCR. Figure 12-6 shows the timing of this operation.
Compare Match Timing
ø
Compare match A
signal
Timer output pin
ø
Compare match
signal
TCNT
Compare match
signal
CMF
ø
TCNT
TCOR
Figure 12-6 Timing of Compare Match Clear
Figure 12-5 Timing of Timer Output
Figure 12-4 Timing of CMF Setting
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Rev.6.00 Oct.28.2004 page 443 of 1016
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