DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 557

• Manufacturer Part Number: DF2398TE20
• Description: IC H8S MCU FLASH 256K 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2398TE20; HD64F2398TE20

15.3.5
Only an internal clock generated by the on-chip baud rate generator can be used as the transmit/receive clock for the Smart
Card interface. The bit rate is set with BRR and the CKS1 and CKS0 bits in SMR. The formula for calculating the bit rate
is as shown below. Table 15-5 shows some sample bit rates.
If clock output is selected by setting CKE0 to 1, a clock with a frequency of 372 times the bit rate is output from the SCK
pin.
B =
Where: N = Value set in BRR (0 N 255)
Table 15-4 Correspondence between n and CKS1, CKS0
Direct convention (SDIR = SINV = O/E = 0)
With the direct convention type, the logic 1 level corresponds to state Z and the logic 0 level to state A, and transfer is
performed in LSB-first order. The start character data above is H'3B.
The parity bit is 1 since even parity is stipulated for the Smart Card.
Inverse convention (SDIR = SINV = O/E = 1)
With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level to state Z, and transfer
is performed in MSB-first order. The start character data above is H'3F.
The parity bit is 0, corresponding to state Z, since even parity is stipulated for the Smart Card.
With the H8S/2357 Group, inversion specified by the SINV bit applies only to the data bits, D7 to D0. For parity bit
inversion, the O/E bit in SMR is set to odd parity mode (the same applies to both transmission and reception).
B = Bit rate (bit/s)
ø = Operating frequency (MHz)
n = See table 15-4
Clock
1488
2
2n–1
ø
(Z)
(Z)
(N + 1)
Ds
Ds
A
A
D7
D0
Z
Z
n
0
1
2
3
D6
D1
10
Z
Z
6
D5
D2
A
A
D4
D3
A
Z
CKS1
0
1
D3
D4
A
Z
D2
D5
A
Z
CKS0
0
1
0
1
D1
D6
A
A
D0
D7
A
A
Rev.6.00 Oct.28.2004 page 527 of 1016
Dp
Dp
Z
Z
(Z)
(Z)
State
State
REJ09B0138-0600H