DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 616

• Manufacturer Part Number: DF2398TE20
• Description: IC H8S MCU FLASH 256K 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2398TE20; HD64F2398TE20

19.7.4
SYSCR2 is an 8-bit readable/writable register that controls on-chip flash memory (in F-ZTAT versions).
SYSCR2 is initialized to H'00 by a reset and in hardware standby mode.
SYSCR2 is available only in the F-ZTAT version. In the masked ROM and ZTAT versions, this register cannot be
written to and will return an undefined value if read.
Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 0.
Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash memory control registers
(FLMCR1, FLMCR2, EBR1, and EBR2). Setting the FLSHE bit to 1 enables read/write access to the flash memory
control registers. If FLSHE is cleared to 0, the flash memory control registers are deselected. In this case, the flash
memory control register contents are retained.
Bits 2 to 0—Reserved: These bits cannot be modified and are always read as 0.
19.7.5
RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating real-time flash memory
programming. RAMER is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software
standby mode. RAMER settings should be made in user mode or user program mode.
Flash memory area divisions are shown in table 19-13. To ensure correct operation of the emulation function, the ROM
for which RAM emulation is performed should not be accessed immediately after this register has been modified. Normal
execution of an access immediately after register modification is not guaranteed.
Bits 7 to 3—Reserved: These bits are always read as 0.
Rev.6.00 Oct.28.2004 page 586 of 1016
REJ09B0138-0600H
Initial value:
Bit
Initial value
Read/Write
System Control Register 2 (SYSCR2)
RAM Emulation Register (RAMER)
Bit 3
FLSHE
0
1
R/W:
Bit:
—
—
—
—
7
0
7
0
Description
Flash control registers deselected in area H'FFFFC8 to H'FFFFCB
Flash control registers selected in area H'FFFFC8 to H'FFFFCB
—
—
—
—
6
0
6
0
—
—
—
—
5
0
5
0
—
—
—
—
4
0
4
0
FLSHE
R/W
—
—
3
0
3
0
RAMS
R/W
—
—
2
0
2
0
RAM1
R/W
—
—
1
0
1
0
RAM0
R/W
—
—
0
0
0
0
(Initial value)