DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 259

• Manufacturer Part Number: DF2398TE20
• Description: IC H8S MCU FLASH 256K 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2398TE20; HD64F2398TE20

DREQ Pin Low Level Activation Timing: Set the DTA bit for the channel for which the DREQ pin is selected to 1.
Figure 7-32 shows an example of DREQ pin low level activated single address mode transfer.
DREQ pin sampling is performed every cycle, with the rising edge of the next ø cycle after the end of the DMABCR write
cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in
the DMAC. Then, when activation is initiated in the DMAC, the request is cleared. After the end of the single cycle,
acceptance resumes, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer
ends.
Figure 7-32 Example of DREQ Pin Low Level Activated Single Address Mode Transfer
Address bus
DMA control
[1]
[2] [5]
[3] [6]
[4] [7]
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Channel
DREQ
DACK
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising
edge of ø, and the request is held.
The request is cleared at the next bus break, and activation is started in the DMAC.
The DMAC cycle is started.
Acceptance is resumed after the single cycle is completed.
(As in [1], the DREQ pin low level is sampled on the rising edge of ø, and the request is held.)
ø
Idle
[1]
Request
Bus release
Minimum of
2 cycles
[2]
[3]
Single
Request clear
Transfer source/
DMA single
destination
period
Acceptance resumes
Idle
[4]
Request
Bus release
Minimum of
2 cycles
[5]
[6]
Single
Request clear
DMA single
Transfer source/
period
destination
Acceptance resumes
Rev.6.00 Oct.28.2004 page 229 of 1016
Idle
[7]
release
Bus
REJ09B0138-0600H