DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 620

• Manufacturer Part Number: DF2398TE20
• Description: IC H8S MCU FLASH 256K 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2398TE20; HD64F2398TE20

Automatic SCI Bit Rate Adjustment
When boot mode is initiated, the H8S/2357 MCU measures the low period of the asynchronous SCI communication data
(H'00) transmitted continuously from the host. The SCI transmit/receive format should be set as follows: 8-bit data, 1 stop
bit, no parity. The MCU calculates the bit rate of the transmission from the host from the measured low period, and
transmits one H'00 byte to the host to indicate the end of bit rate adjustment. The host should confirm that this adjustment
end indication (H'00) has been received normally, and transmit one H'55 byte to the MCU. If reception cannot be
performed normally, initiate boot mode again (reset), and repeat the above operations. Depending on the host’s
transmission bit rate and the MCU’s system clock frequency, there will be a discrepancy between the bit rates of the host
and the MCU. To ensure correct SCI operation, the host’s transfer bit rate should be set to (4,800, or 9,600) bps.
Table 19-15 shows typical host transfer bit rates and system clock frequencies for which automatic adjustment of the
MCU’s bit rate is possible. The boot program should be executed within this system clock range.
Table 19-15 System Clock Frequencies for which Automatic Adjustment of H8S/2357 Bit Rate is Possible
On-Chip RAM Area Divisions in Boot Mode: In boot mode, the 2 kbytes area from H'FFDC00 to H'FFE3FF is reserved
for use by the boot program, as shown in figure 19-17. The area to which the programming control program is transferred
is H'FFE400 to H'FFFB7F. The boot program area can be used when the programming control program transferred into
RAM enters the execution state. A stack area should be set up as required.
Rev.6.00 Oct.28.2004 page 590 of 1016
REJ09B0138-0600H
Host Bit Rate
9600 bps
4800 bps
Start
bit
Figure 19-16 Automatic SCI Bit Rate Adjustment
D0
Low period (9 bits) measured (H'00 data)
System Clock Frequency for which Automatic Adjustment
of H8S/2357 Bit Rate is Possible
8 to 20 MHz
4 to 20 MHz
D1
D2
D3
D4
D5
D6
D7
(1 or more bits)
High period
Stop
bit