DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 538

• Manufacturer Part Number: DF2398TE20
• Description: IC H8S MCU FLASH 256K 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2398TE20; HD64F2398TE20

In serial transmission, the SCI operates as described below.
[1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the
[2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set
[3] The SCI checks the TDRE flag at the timing for sending the MSB (bit 7).
[4] After completion of serial transmission, the SCK pin is fixed.
Figure 14-17 shows an example of SCI operation in transmission.
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data from TDR to TSR.
to 1 at this time, a transmit data empty interrupt (TXI) is generated.
When clock output mode has been set, the SCI outputs 8 serial clock pulses. When use of an external clock has been
specified, data is output synchronized with the input clock.
The serial transmit data is sent from the TxD pin starting with the LSB (bit 0) and ending with the MSB (bit 7).
If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission of the next frame is
started.
If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the MSB (bit 7) is sent, and the TxD pin maintains its
state.
If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated.
Serial clock
Serial data
TDRE
TEND
TXI interrupt
request generated
Figure 14-17 Example of SCI Operation in Transmission
interrupt service routine
Data written to TDR
cleared to 0 in TXI
Bit 7
and TDRE flag
Transfer direction
Bit 0
1 frame
TXI interrupt
request generated
Bit 7
Bit 0
Bit 1
Bit 6
TEI interrupt
request generated
Bit 7