DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 275

• Manufacturer Part Number: DF2398TE20
• Description: IC H8S MCU FLASH 256K 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2398TE20; HD64F2398TE20

Bit 1—DTC Transfer Mode Select (DTS): Specifies whether the source side or the destination side is set to be a repeat
area or block area, in repeat mode or block transfer mode.
Bit 0—DTC Data Transfer Size (Sz): Specifies the size of data to be transferred.
8.2.2
MRB is an 8-bit register that controls the DTC operating mode.
Bit 7—DTC Chain Transfer Enable (CHNE): Specifies chain transfer. With chain transfer, a number of data transfers
can be performed consecutively in response to a single transfer request.
In data transfer with CHNE set to 1, determination of the end of the specified number of transfers, clearing of the interrupt
source flag, and clearing of DTCER is not performed.
Bit 6—DTC Interrupt Select (DISEL): Specifies whether interrupt requests to the CPU are disabled or enabled after a
data transfer.
Bits 5 to 0—Reserved: These bits have no effect on DTC operation in the H8S/2357 Group, and should always be written
with 0.
Bit
Initial value :
R/W
DTC Mode Register B (MRB)
Bit 1
DTS
0
1
Bit 0
Sz
0
1
Bit 7
CHNE
0
1
Bit 6
DISEL
0
1
:
:
CHNE
Unde-
fined
—
7
Description
Destination side is repeat area or block area
Source side is repeat area or block area
Description
Byte-size transfer
Word-size transfer
Description
End of DTC data transfer (activation waiting state is entered)
DTC chain transfer (new register information is read, then data is transferred)
Description
After a data transfer ends, the CPU interrupt is disabled unless the transfer counter is
0 (the DTC clears the interrupt source flag of the activating interrupt to 0)
After a data transfer ends, the CPU interrupt is enabled (the DTC does not clear the
interrupt source flag of the activating interrupt to 0)
DISEL
Unde-
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6
Unde-
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—
5
Unde-
fined
—
—
4
Unde-
fined
—
—
3
Unde-
fined
—
—
2
Unde-
fined
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Rev.6.00 Oct.28.2004 page 245 of 1016
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REJ09B0138-0600H