DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 185

• Manufacturer Part Number: DF2398TE20
• Description: IC H8S MCU FLASH 256K 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2398TE20; HD64F2398TE20

(3) Relationship between Chip Select (CS) Signal and Read (RD) Signal
Depending on the system’s load conditions, the RD signal may lag behind the CS signal. An example is shown in figure 6-
33.
In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap between the bus cycle A RD
signal and the bus cycle B CS signal.
Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and CS signals.
In the initial state after reset release, idle cycle insertion (b) is set.
6.8.2
When DRAM space is accessed, the ICIS0 and ICIS1 bit settings are disabled. In the case of consecutive reads between
different areas, for example, if the second access is a DRAM access, only a T
timing in this case is shown in figure 6-34.
However, in burst access in RAS down mode these settings are enabled, and an idle cycle is inserted. The timing in this
case is shown in figures 6-35 (a) and (b).
Usage Notes
Address bus
CS (area A)
CS (area B)
RD
Possibility of overlap between
CS (area B) and RD
ø
Figure 6-33 Relationship between Chip Select (CS) and Read (RD)
(a) Idle cycle not inserted
T
1
Bus cycle A
(ICIS1 = 0)
T
2
T
3
Bus cycle B
T
1
T
2
Address bus
CS (area A)
CS (area B)
RD
ø
T
p
1
Bus cycle A
(b) Idle cycle inserted
cycle is inserted, and a T
T
(Initial value ICIS1 = 1)
Rev.6.00 Oct.28.2004 page 155 of 1016
2
T
3
T
I
Bus cycle B
T
1
REJ09B0138-0600H
I
T
cycle is not. The
2