R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 1025

• Manufacturer Part Number: R8A77850ADBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

20.3.14 CL Status Register (CLSR)
CLSR is in the CL register block and indicates the internal states of the CL.
Initial value:
Initial value:
Bit
31 to 4
3
2
1, 0
R/W:
R/W:
BIt:
BIt:
Bit Name
⎯
CLSR_EXE
CL_CFF
CL_CFS
31
15
⎯
⎯
⎯
⎯
0
0
30
14
⎯
⎯
⎯
⎯
0
0
29
13
⎯
⎯
⎯
⎯
0
0
Initial
Value
All 0
0
0
0
28
⎯
⎯
12
⎯
⎯
0
0
R/W
⎯
R
R
R
27
⎯
⎯
11
⎯
⎯
0
0
26
10
⎯
⎯
⎯
⎯
0
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
CL execution state display
0: Stopped
1: Executing
CL_CF (command FIFO) status display
Indicates the state of command buffer reception.
0: Command receivable
1: Command buffer full
Command pointer status display
00: CL_CF command parameter 1 setting wait state
01: CL_CF command parameter 2 setting wait state
10: CL_CF command parameter 3 setting wait state
11: CL_CF command parameter 4 setting wait state
25
⎯
⎯
⎯
⎯
0
9
0
24
⎯
⎯
⎯
⎯
0
8
0
20. Graphics Data Translation Accelerator (GDTA)
23
⎯
⎯
⎯
⎯
0
7
0
Rev.1.00 Jan. 10, 2008 Page 993 of 1658
22
⎯
⎯
⎯
⎯
0
6
0
21
⎯
⎯
⎯
⎯
0
5
0
20
⎯
⎯
⎯
⎯
0
4
0
CLSR_
EXE
19
⎯
⎯
R
0
3
0
REJ09B0261-0100
CL_CFF
18
⎯
⎯
R
0
2
0
17
⎯
⎯
R
0
1
0
CL_CFS
16
⎯
⎯
R
0
0
0