R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 369

• Manufacturer Part Number: R8A77850ADBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

10.5
10.5.1
The sequence of interrupt operations is described below. Figure 10.4 shows a flowchart of the
operations.
1. Interrupt request sources send interrupt request signals to the INTC.
2. The INTC selects the interrupt with the highest priority among the interrupts that have been
3. The priority level of the interrupt selected by the INTC is compared with the interrupt mask
4. The CPU accepts an interrupt at the next break between instructions.
5. The interrupt source code is set in the interrupt event register (INTEVT).
6. The SR and program counter (PC) are saved in SSR and SPC, respectively. At that time, R15
7. The BL, MD, and RB bits in SR are set to 1.
8. Execution jumps to the start address of the interrupt exception handling routine (the sum of the
In the exception handling routine, the value of INTEVT is branched as an offset. This easily
enables to branch the exception handling routine to handling routine for each interrupt source.
Notes: 1. When the INTMU bit in CPUOPM is set to 1, the interrupt mask level (IMASK) in SR
sent, according to the priority set in INTPRI and INT2PRI0 to INT2PRI9. Lower priority
interrupts are held as pending interrupts. If two of the interrupts have the same priority level or
multiple interrupts are generated by a single module, the interrupt with the highest priority is
selected according to table 10.13.
level (IMASK) set in SR of the CPU. Only the interrupt with a higher priority than the IMASK
bit is accepted, and an interrupt request signal is sent to the CPU.
is saved in SGR.
value set in the vector base register (VBR) and H'0000 0600).
2. The interrupt source flag should be cleared during exception handling routine. To
3. The IRQ interrupts, IRL interrupts, on-chip peripheral module interrupts are initialized
Operation
Interrupt Sequence
is automatically set to the level of the accepted interrupt. When the INTMU bit in
CPUOPM is cleared to 0, the value of the IMASK in SR is not affected by the accepted
interrupt.
ensure that an interrupt source which should have been cleared is not erroneously
accepted again, read the interrupt source flag after it has been cleared, and wait for the
time shown in table 10.14. Then, clear the BL bit or execute an RTE instruction.
to the interrupt masking state by a power-on reset. Therefore, clear the interrupt
masking for each interrupt , INTMSK0, INTMSK1, and INT2MSKR by using
INTMSKCLR0, INTMSKCLR1, and INT2MSKCLR.
Rev.1.00 Jan. 10, 2008 Page 337 of 1658
10. Interrupt Controller (INTC)
REJ09B0261-0100