R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 1390

IC SUPERH MPU ROMLESS 436-BGA

R8A77850ADBGV#RD0Z

Manufacturer Part Number
R8A77850ADBGV#RD0Z
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R8A77850ADBGV#RD0Z

Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

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R8A77850ADBGV#RD0ZR8A77850ADBGV
Manufacturer:
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Part Number:
R8A77850ADBGV#RD0Z
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27. NAND Flash Memory Controller (FLCTL)
Rev.1.00 Jan. 10, 2008 Page 1358 of 1658
REJ09B0261-0100
Bit
3
2
1
0
Bit Name
BTOINTE
TEINTE
TRINTE1
TRINTE0
Initial
Value
0
0
0
0
R/W
RW
R/W
R/W
R/W
Transfer End Interrupt Enable
Description
Interrupt Enable at Timeout Error
Enables or disables an interrupt request to the CPU
when a timeout error has occurred.
0: Disables the interrupt request to the CPU by a
1: Enables the interrupt request to the CPU by a
Enables or disables an interrupt request to the CPU
when a transfer has been ended (TREND bit in
FLTRCR).
0: Disables an interrupt to the CPU at the end of a
1: Enables an interrupt to the CPU at the end of a
FLECFIFO Transfer Request Enable to CPU
Enables or disables an interrupt request to the CPU by
a transfer request from FLECFIFO.
0: Disables an interrupt request to the CPU by a
1: Enables an interrupt request to the CPU by a transfer
When the DMA transfer is enabled, this bit should be
cleared to 0.
FLDTFIFO Transfer Request Enable to CPU
Enables or disables an interrupt request to the CPU by
a transfer request from FLDTFIFO.
0: Disables an interrupt request to the CPU by a
1: Enables an interrupt request to the CPU by a transfer
When the DMA transfer is enabled, this bit should be
cleared to 0.
transfer
transfer
timeout error
timeout error
transfer request from FLECFIFO.
request from FLECFIFO.
transfer request from FLDTFIFO
request from FLDTFIFO

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