R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 986

• Manufacturer Part Number: R8A77850ADBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

19. Display Unit (DU)
19.4.16 Sync Mode
In order to facilitate synchronization with external equipment, in addition to master mode, a TV
synchronization function is provided. Selection of master mode and TV sync mode is performed
using the TVM bit in DSYSR. Regardless of the synchronization method, the position of the
falling edge of the vertical sync signal (VSYNC) set by VSPR is detected and is reflected in the
FRM bit and VBK bit in DSSR.
Master Mode (Internal Sync Mode): By setting the period and pulse width of the horizontal and
vertical sync signals (HSYNC, VSYNC) in the display timing generation register, the
corresponding waveforms are output. Also, display data is output in sync with these signals.
When in interlaced sync mode and interlaced sync & video mode, a signal is output to the ODDF
pin indicating odd/even fields.
TV Sync Mode (External Sync Mode): In TV sync mode, display data is output in sync with a
horizontal sync signal and vertical sync signal (EXHSYNC, EXVSYNC) input from a TV, video,
or other external sync signal generation circuit. Display data is output with reference to the falling
edge of the EXHSYNC signal and the rising edge of the EXVSYNC signal.
The horizontal sync signal, vertical sync signal, and clock signal from the external sync signal
generation circuit are input to the HSYNC, VSYNC, and DCLKIN pin, respectively. CSYNC is at
high level. When in interlaced sync mode and interlaced sync & video mode, a signal should be
input to the ODDF pin indicating odd/even fields. When in non-interlaced mode, the input to the
ODDF pin should be fixed at low level or at high level.
When operating the unit in TV sync mode also, values must be set in HCR, HSWR, VCR, and
VSPR (display timing generation registers).
When the EXVSYNC signal is input, either before or after completion of display of the display
size portion set in the display unit (DU), the display unit (DU) performs vertical display
completion operation and transitions to control for the next screen. When the EXVSYNC signal is
not input, the unit continues to wait for the EXVSYNC signal while remaining in the vertical
blanking interval (auto-control is not performed). Similarly, when the EXHSYNC signal is input
the display unit (DU) performs horizontal display completion operation and transitions to control
for the next raster line; but if the EXHSYNC signal is not input, the unit continues to wait for the
EXHSYNC signal while remaining in the horizontal blanking interval (auto-control is not
performed).
Rev.1.00 Jan. 10, 2008 Page 954 of 1658
REJ09B0261-0100