R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 338

• Manufacturer Part Number: R8A77850ADBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

10. Interrupt Controller (INTC)
Note: The registers in the modules that indicate generation of interrupt requests are as follows.
Rev.1.00 Jan. 10, 2008 Page 306 of 1658
REJ09B0261-0100
Module
DMAC
WDT:
TMU:
SCIF:
HSPI:
SIOF:
MMCIF: INTSTR0 to INTSTR2
DU:
SSI:
HAC:
FLCTL: FLINTDMACR, FLTRCR
WDTCSR
TCR0 to TCR5
SCFSR0 to SCFSR6, SCLSR0 to SCLSR6
SPSR
SISTR
DSSR
SSISR
HACTSR, HACRSR
Interrupt sources
DMAE0, DMAE1
Interrupt sources
DMINT0 to
DMINT11
Relation between Setting/Clearing Interrupt Source of
Module and Indication by INT2A0 and INT2A1
When the DMAE0 or DMAE1 interrupt source bit (i.e. the AE bit
in DMAOR0 or DMAOR1) is set, the same interrupt status
information is read from registers DMAOR0 and DMAOR1 and
registers INT2A0 and INT2A1. This means that the time
required for reflection in INT2A0 and INT2A1 is guaranteed by
hardware.
When the DMAE0 or DMAE1 interrupt source is cleared, the
time required for reflection in INT2A0 and INT2A1 is
guaranteed by dummy reading DMAOR0 or DMAOR1 once
after writing to DMAOR0 or DMAOR1.
Setting of the HE and TE bits in CHCR0 to CHCR11 and output
of interrupt request to the INTC take place with different timing.
For details, see section 14, Direct Memory Access Controller
(DMAC).
When interrupt sources, DMINT0 to DMINT11 (corresponding
to bits HE and TE in CHCR0 to CHCR11) are cleared, the time
required for reflection in INT2A0 and INT2A1 is guaranteed by
dummy-reading CHCR0 to CHCR11 once after writing to
CHCR0 to CHCR11 that indicate generation of interrupt
requests.