R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 1370

• Manufacturer Part Number: R8A77850ADBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

27. NAND Flash Memory Controller (FLCTL)
(5)
• On-chip 224-byte FLDTFIFO for data transfer of flash memory
• On-chip 32-byte FLECFIFO for data transfer of a control code
• Flag bit for detection of overrun or underrun during access from the CPU or DMA
(6)
• By individually specifying the transfer destinations of data and control code of flash memory
(7)
• Registers include 32-bit registers and an 8-bit register. Read from or write to the register with
• The access size of FIFO is 32 bits (4 bytes). In reading, set the byte number to a multiple of
(8)
• The operating frequency of the FLCTL pins can be specified by the FCKSEL bit and the
• The operating clock, FCLK, on the pins for the NAND-type flash memory is used by dividing
• In NAND-type flash memory, the FRE and FWE pins operate with the FCLK specified by
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to the DMA controller, data and control code can be transferred to different areas.
the specified access size.
four. In writing, set the byte number to a multiple of four in writing.
QTSEL bit in FLCMNCR, regardless of the operating frequency of the peripheral bus.
the operating clock of the peripheral bus (a peripheral clock).
FLCMNCR. To ensure the setup time, this operating frequencies should not exceed the
maximum operating frequency of memory to be connected.
Data Transfer FIFO
DMA Transfer
Access Size
Access Time