R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 298

• Manufacturer Part Number: R8A77850ADBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

10. Interrupt Controller (INTC)
10.1.1
The basic flow of exception handling for interrupts is as follows.
In interrupt exception handling, the contents of the program counter (PC), status register (SR), and
general register 15 (R15) are saved in the saved program counter (SPC), saved status register
(SSR), and saved general register15 (SGR), and the CPU starts execution of the interrupt
exception handling routine at the corresponding vector address. An interrupt exception handling
routine is a program written by the user to handle a specific exception. The interrupt exception
handling routine is terminated and control returned to the original program by executing a return-
from-exception instruction (RTE). This instruction restores the contents of PC and SR and returns
control to the normal processing routine at the point at which the exception occurred. The contents
of SGR are not written back to R15 by the RTE instruction.
1. The contents of the PC, SR and R15 are saved in SPC, SSR and SGR, respectively.
2. The block (BL) bit in SR is set to 1.
3. The mode (MD) bit in SR is set to 1.
4. The register bank (RB) bit in SR is set to 1.
5. In a reset, the FPU disable (FD) bit in SR is cleared to 0.
6. The exception code is written to bits 13 to 0 of the interrupt event register (INTEVT).
7. Processing jumps to the start address of the interrupt exception handling routine, vector base
8. The processing branches to the corresponding exception handling vector address and the
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register (VBR) + H'600.
When the INTMU bit in CPOOPM is set to 1, the interrupt mask level (IMASK) in SR is
automatically modified to the level of the accepted interrupt.
exception handling routine starts.
Interrupt Method