R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 1147

• Manufacturer Part Number: R8A77850ADBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bit
5
4
Bit Name
SAERR
FSERR
Initial
Value
0
0
R/W
R/W
R/W
Description
Slot Assign Error
0: Indicates that no slot assign error occurs
1: Indicates that a slot assign error occurs
A slot assign error occurs when the settings in SITDAR,
SIRDAR, and SICDAR overlap.
If a slot assign error occurs, the SIOF does not transmit
data to the SIOF_TXD pin and does not receive data
from the SIOF_RXD pin. Note that the SIOF does not
clear the TXE bit or RXE bit in SICTR at a slot assign
error.
•
•
•
Frame Synchronization Error
0: Indicates that no frame synchronization error occurs
1: Indicates that a frame synchronization error occurs
A frame synchronization error occurs when the next
frame synchronization timing appears before the
previous data or control data transfers have been
completed.
If a frame synchronization error occurs, the SIOF
performs transmission or reception for slots that can be
transferred.
•
•
•
This bit is valid when the TXE bit or RXE bit in
SICTR is 1.
When 1 is written to this bit, the contents are
cleared. Writing 0 to this bit is invalid.
To enable the issuance of this interrupt source, set
the SAERRE bit in SIIER to 1.
This bit is valid when the TXE or RXE bit in SICTR
is 1.
When 1 is written to this bit, the contents are
cleared. Writing 0 to this bit is invalid.
To enable the issuance of this interrupt source, set
the FSERRE bit in SIIER to 1.
Rev.1.00 Jan. 10, 2008 Page 1115 of 1658
22. Serial I/O with FIFO (SIOF)
REJ09B0261-0100