R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 444

• Manufacturer Part Number: R8A77850ADBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

11. Local Bus State Controller (LBSC)
11.5.4
Burst ROM Interface
When the TYPE bit in CSnBCR is set to 010, a burst ROM can be connected to areas 0 to 6. The
burst ROM interface provides high-speed access to ROM that has a burst access function. The
burst access timing of burst ROM is shown in figure 11.12. The wait cycle is set to 0. Although
the access is similar to that of the SRAM interface, only the address is changed when the first
cycle ends and then the next access is started. When 8-bit ROM is used, the number of consecutive
accesses can be set to 4, 8, 16, or 32 times through bits BST2 to BST0 in CSnBCR (n = 0 to 6).
Similarly, when 16-bit ROM is used, 4, 8 or 16 times can be set; when 32-bit ROM is used, 4 or 8
times can be set.
The RDY signal is always sampled when the wait cycle is set to 1 or more. Even when no wait is
specified in the burst ROM settings, the second and subsequent accesses are performed with two
cycles as shown in figure 11.13.
Writing to this interface is performed in the same way as for the SRAM interface.
In a 32-byte transfer, a total of 32 bytes are transferred continuously according to the set bus
width. The first access is performed on the data for which an access request is issued, and the
remaining accesses are performed on wraparound method according to the set bus width. The bus
is not released during this transfer.
Figure 11.14 shows the timing when the burst ROM is used and setup/hold is specified by
CSnWCR.
Rev.1.00 Jan. 10, 2008 Page 412 of 1658
REJ09B0261-0100