R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 77

• Manufacturer Part Number: R8A77850ADBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

This LSI's instruction set is implemented with 16-bit fixed-length instructions. This LSI can use
byte (8-bit), word (16-bit), longword (32-bit), and quadword (64-bit) data sizes for memory
access. Single-precision floating-point data (32 bits) can be moved to and from memory using
longword or quadword size. Double-precision floating-point data (64 bits) can be moved to and
from memory using longword size. When this LSI moves byte-size or word-size data from
memory to a register, the data is sign-extended.
3.1
(1)
At the start of instruction execution, the PC indicates the address of the instruction itself.
(2)
This LSI has a load-store architecture in which operations are basically executed using registers.
Except for bit-manipulation operations such as logical AND that are executed directly in memory,
operands in an operation that requires memory access are loaded into registers and the operation is
executed between the registers.
(3)
Except for the two branch instructions BF and BT, this LSI's branch instructions and RTE are
delayed branches. In a delayed branch, the instruction following the branch is executed before the
branch destination instruction.
(4)
This execution slot following a delayed branch is called a delay slot. For example, the BRA
execution sequence is as follows:
PC
Load-Store Architecture
Delayed Branches
Delay Slot
Execution Environment
Section 3 Instruction Set
Rev.1.00 Jan. 10, 2008 Page 45 of 1658
REJ09B0261-0100
3. Instruction Set