R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 25

• Manufacturer Part Number: R8A77850ADBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

21.4 Operation ......................................................................................................................... 1071
21.5 SCIF Interrupt Sources and the DMAC ........................................................................... 1094
21.6 Usage Notes ..................................................................................................................... 1096
Section 22 Serial I/O with FIFO (SIOF)
22.1 Features............................................................................................................................ 1099
22.2 Input/Output Pins ............................................................................................................. 1101
22.3 Register Descriptions ....................................................................................................... 1102
22.4 Operation ......................................................................................................................... 1128
Section 23 Serial Peripheral Interface (HSPI)
23.1 Features............................................................................................................................ 1151
21.3.12 Serial Port Register n (SCSPTR) ...................................................................... 1066
21.3.13 Line Status Register n (SCLSR) ....................................................................... 1069
21.3.14 Serial Error Register n (SCRER) ...................................................................... 1070
21.4.1
21.4.2
21.4.3
22.3.1
22.3.2
22.3.3
22.3.4
22.3.5
22.3.6
22.3.7
22.3.8
22.3.9
22.3.10 Clock Select Register (SISCR) ......................................................................... 1122
22.3.11 Transmit Data Assign Register (SITDAR) ....................................................... 1123
22.3.12 Receive Data Assign Register (SIRDAR) ........................................................ 1125
22.3.13 Control Data Assign Register (SICDAR) ......................................................... 1126
22.4.1
22.4.2
22.4.3
22.4.4
22.4.5
22.4.6
22.4.7
22.4.8
22.4.9
Overview .......................................................................................................... 1071
Operation in Asynchronous Mode .................................................................... 1074
Operation in Clocked Synchronous Mode ........................................................ 1085
Mode Register (SIMDR) .................................................................................. 1104
Control Register (SICTR)................................................................................. 1106
Transmit Data Register (SITDR) ...................................................................... 1108
Receive Data Register (SIRDR) ....................................................................... 1109
Transmit Control Data Register (SITCR) ......................................................... 1110
Receive Control Data Register (SIRCR) .......................................................... 1111
Status Register (SISTR).................................................................................... 1112
Interrupt Enable Register (SIIER) .................................................................... 1118
FIFO Control Register (SIFCTR) ..................................................................... 1120
Serial Clocks..................................................................................................... 1128
Serial Timing .................................................................................................... 1129
Transfer Data Format........................................................................................ 1131
Register Allocation of Transfer Data ................................................................ 1133
Control Data Interface ...................................................................................... 1135
FIFO.................................................................................................................. 1137
Transmit and Receive Procedures..................................................................... 1139
Interrupts........................................................................................................... 1144
Transmit and Receive Timing........................................................................... 1146
...................................................................... 1099
............................................................ 1151
Rev.1.00 Jan. 10, 2008 Page xxiii of xxx
REJ09B0261-0100