R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 773

• Manufacturer Part Number: R8A77850ADBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

15.4.1
FRQCR0 is a 32-bit readable and partially writable register that executes a sequence for changing
the frequency of each clock. After the sequence is executed, FRQCR0 is automatically cleared to
0. FRQCR0 can only be accessed in longwords.
To write to FRQCR0, set the code value (H'CF) in the upper byte and use the longword. No other
code values can be written. The code value is always read as 0.
FRQCR0 is initialized by only a power-on reset via the PRESET pin or a WDT overflow.
Initial value:
Initial value:
Bit
31 to 24 ⎯
23 to 1
0
R/W:
R/W:
BIt:
BIt:
Frequency Control Register 0 (FRQCR0)
Bit Name
⎯
FRQE
R/W
31
15
⎯
R
0
0
R/W
30
14
⎯
R
0
0
R/W
29
13
⎯
R
0
0
Initial
Value
All 0
All 0
0
Code value (H'CF)
R/W
28
12
⎯
R
0
0
R/W
R/W
R/W
R
R/W
27
11
⎯
R
0
0
R/W
26
10
⎯
R
0
0
Description
Code value (H'CF)
These bits are always read as 0. The write value
should always be H'CF.
Reserved
These bits are always read as 0. The write value
should always be 0.
Frequency Change Sequence Enabled
Enables the execution of a sequence that changes the
frequency of each clock according to the value set in
FRQCR1. After executing the sequence, this bit is
automatically cleared to 0.
0: Execution of a sequence that changes the frequency
1: Execution of a sequence that changes the frequency
Note: Some division ratio settings are prohibited. When
R/W
25
⎯
is disabled.
is enabled.
R
0
9
0
a value that is not shown in Tables 15.8 to 15.11
is set in FRQCR1, do not set 1 in FRQE.
R/W
24
⎯
R
0
8
0
23
⎯
⎯
R
R
0
7
0
Rev.1.00 Jan. 10, 2008 Page 741 of 1658
22
⎯
⎯
R
R
0
6
0
21
⎯
⎯
R
R
0
5
0
15. Clock Pulse Generator (CPG)
20
⎯
⎯
R
R
0
4
0
19
⎯
⎯
R
R
0
3
0
REJ09B0261-0100
18
⎯
⎯
R
R
0
2
0
17
⎯
⎯
R
R
0
1
0
FRQE
R/W
16
⎯
R
0
0
0