R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 277

IC SUPERH MPU ROMLESS 436-BGA

R8A77850ADBGV#RD0Z

Manufacturer Part Number
R8A77850ADBGV#RD0Z
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R8A77850ADBGV#RD0Z

Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

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R8A77850ADBGV#RD0ZR8A77850ADBGV
Manufacturer:
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10 000
Company:
Part Number:
R8A77850ADBGV#RD0Z
Manufacturer:
Renesas Electronics America
Quantity:
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Table 9.3
• Ports
• Priority
Address Space
Virtual address
Physical address
The CPU can access the P4 area in the virtual address space (when SR.MD = 1) or on-chip
memory area (when SR.MD = 0 and RAMCR.RMD = 1). Access operations involving these
addresses are always non-cacheable.
The U memory has three independent read/write ports and is connected to the operand bus, the
cache/RAM internal bus, and the SuperHyway bus. The operand bus is used when the U
memory is accessed through operand read access. The cache/RAM internal bus is used when
the U memory is accessed through instruction fetch and operand write access. The
SuperHyway bus is used for U memory access from the SuperHyway bus master module.
In the event of simultaneous accesses to the U memory from different buses, the access
requests are processed according to priority. The priority order is: SuperHyway bus >
cache/RAM internal bus > operand bus.
U Memory Addresses
Memory Address
H'E55F 0000 to H'E560 FFFF
H'E55F 0000 to H'E560 FFFF
Rev.1.00 Jan. 10, 2008 Page 245 of 1658
9. On-Chip Memory
REJ09B0261-0100

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