R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 1049

• Manufacturer Part Number: R8A77850ADBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

(3)
Various initial settings are made by the CPU, and processing is started. The processing procedure
is the same for YUYV conversion mode and for ARGB conversion mode, except that in ARGB
conversion mode the data of the color conversion table must be prepared in buffer RAM 0. The
procedure is described below.
No. Operation
(4) ARGB
(5) Output data
conversion
writing
CL Processing Procedure
Description
ARGB data is generated from color information read from buffer RAM 0
using the following formula, and the converted data is output in the format
shown in the display image of figure 20.4. ARGB conversion is performed
according to the following conversion logic.
A = The result of computation of clip_0_255((A+16)>> 5) for unsigned 16-bit
data (11 integer bits, 5 decimal bits) read from RAM 0 is output.
R = clip_0_255((Y1 +
G = clip_0_255((Y1 + U0 + V1 + 16) >> 5);
B = clip_0_255((Y1 + U1
When Y1 = 0, the conversion result is R, G, B = 0.
clip_0_255: 8-bit saturation calculation (0 ≤ x ≤ 255) (the sign is determined
by the uppermost bit (bit 15))
The converted data is output according to the conversion data output order
in the display image of figure 20.4, regardless of the output destination.
Converted data is output by the size 4 x the frame width specified by
CLWR, rounded up to an integral multiple of 32 bytes.
Because output data is transferred in 32 byte units, one line of output data,
including output padding, should be made an integral multiple of 32 bytes.
Padding data other than that used for adjustment for the 32-byte boundary
is not output.
The output data write address for the next line output is calculated by
adding, to the current write address, the size of the padding data that is
specified as the output padding size for each line.
V0 + 16) >> 5);
20. Graphics Data Translation Accelerator (GDTA)
+ 16) >> 5);
Rev.1.00 Jan. 10, 2008 Page 1017 of 1658
REJ09B0261-0100