ADSP-21161NKCAZ100 Analog Devices Inc, ADSP-21161NKCAZ100 Datasheet - Page 10

• Manufacturer Part Number: ADSP-21161NKCAZ100
• Description: IC,DSP,32-BIT,CMOS,BGA,225PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-21161NKCAZ100

• Rohs Compliant: YES
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 100MHz
• Non-volatile Memory: External
• On-chip Ram: 128kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.80V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 225-MBGA, 225-Mini-BGA
• Device Core Size: 32b
• Architecture: Enhanced Harvard
• Format: Floating Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 128KB
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (min): 1.71/3.13V
• Operating Supply Voltage (max): 1.89/3.47V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADSP21161NKCAZ100

ADSP-21161N
provides full-speed emulation, allowing inspection and modifi-
cation of memory, registers, and processor stacks. Nonintrusive
in-circuit emulation is assured by the use of the processor’s
JTAG interface—the emulator does not affect target system
loading or timing.
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the SHARC processor family. Hard-
ware tools include SHARC PC plug-in cards. Third party
software tools include DSP libraries, real-time operating sys-
tems, and block diagram design tools.
Designing an Emulator-Compatible DSP Board (Target)
The Analog Devices DSP Tools family of emulators are tools
that every DSP developer needs to test and debug hardware and
software systems. Analog Devices has supplied an IEEE 1149.1
JTAG Test Access Port (TAP) on each JTAG DSP. The emulator
uses the TAP to access the internal features of the DSP, allowing
the developer to load code, set breakpoints, observe variables,
observe memory, and examine registers. The DSP must be
halted to send data and commands, but once an operation has
been completed by the emulator, the DSP system is set running
at full speed with no impact on system timing.
To use these emulators, the target’s design must include the
interface between an Analog Devices JTAG DSP and the emula-
tion header on a custom DSP target board.
Target Board Header
The emulator interface to an Analog Devices JTAG DSP is a
14-pin header, as shown in
this header on the target board in order to communicate with
the emulator. The interface consists of a standard dual row
0.025" square post header, set on 0.1" 0.1" spacing, with a min-
imum post length of 0.235". Pin 3 is the key position used to
prevent the pod from being inserted backwards. This pin must
be clipped on the target board.
Also, the clearance (length, width, and height) around the
header must be considered. Leave a clearance of at least 0.15"
and 0.10" around the length and width of the header, and
reserve a height clearance to attach and detach the pod
connector.
As shown in
There are the standard JTAG signals TMS, TCK, TDI, TDO,
TRST, and EMU used for emulation purposes (via an emulator).
There are also secondary JTAG signals BTMS, BTCK, BTDI,
and BTRST that are optionally used for board-level (boundary
scan) testing.
When the emulator is not connected to this header, place jump-
ers across BTMS, BTCK, BTRST, and BTDI as shown in
Figure
allow the DSP to run free. Remove all the jumpers when con-
necting the emulator to the JTAG header.
8. This holds the JTAG signals in the correct state to
Figure
7, there are two sets of signals on the header.
Figure
7. The customer must supply
Rev. B | Page 10 of 60 | November 2009
Figure 7. JTAG Target Board Connector for JTAG Equipped Analog Devices
Figure 8. JTAG Target Board Connector with No
KEY (NO PIN)
KEY (NO PIN)
BTRST
BTMS
BTCK
GND
BTDI
GND
BTRST
DSP (Jumpers in Place)
BTMS
BTCK
GND
BTDI
GND
Local Boundary Scan
11
13
1
3
5
7
9
TOP VIEW
11
13
1
3
5
7
9
9
TOP VIEW
14
10
12
2
4
6
8
14
10
12
2
4
6
8
EMU
GND
TMS
TCK
TRST
TDI
TDO
EMU
TRST
TDI
TDO
GND
TMS
TCK