ADSP-21161NKCAZ100 Analog Devices Inc, ADSP-21161NKCAZ100 Datasheet - Page 45

• Manufacturer Part Number: ADSP-21161NKCAZ100
• Description: IC,DSP,32-BIT,CMOS,BGA,225PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-21161NKCAZ100

• Rohs Compliant: YES
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 100MHz
• Non-volatile Memory: External
• On-chip Ram: 128kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.80V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 225-MBGA, 225-Mini-BGA
• Device Core Size: 32b
• Architecture: Enhanced Harvard
• Format: Floating Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 128KB
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (min): 1.71/3.13V
• Operating Supply Voltage (max): 1.89/3.47V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADSP21161NKCAZ100

Link Ports
Calculation of link receiver data setup and hold relative to link
clock is required to determine the maximum allowable skew
that can be introduced in the transmission path between
LDATA and LCLK. Setup skew is the maximum delay that can
be introduced in LDATA relative to LCLK,
(setup skew = t
maximum delay that can be introduced in LCLK relative to
LDATA, (hold skew = t
Table 28. Link Ports — Receive
1
Parameter
Timing Requirements
t
t
t
t
t
Switching Characteristics
t
LACK goes low with t
SLDCL
HLDCL
LCLKIW
LCLKRWL
LCLKRWH
DLALC
LCLKTWH
Data Setup Before LCLK Low
Data Hold After LCLK Low
LCLK Period
LCLK Width Low
LCLK Width High
LACK Low Delay After LCLK High
LDAT7-0
LACK (OUT)
LCLK
DLALC
RECEIVE
relative to rise of LCLK after first nibble, but does not go low if the receiver's link buffer is not about to fill.
min – t
LCLKTWL
DLDCH
min – t
– t
HLDCH
SLDCL
). Hold skew is the
– t
t
LCLKRWH
HLDCL
1
Rev. B | Page 45 of 60 | November 2009
). Calcula-
Figure 31. Link Ports—Receive
t
SLDCL
IN
t
LCLKIW
t
tions made directly from speed specifications will result in
unrealistically small skew times because they include multiple
tester guardbands. The setup and hold skew times shown below
are calculated to include only one tester guardband.
ADSP-21161N Setup Skew = 1.5 ns max
ADSP-21161N Hold Skew = 1.5 ns max
Note that there is a two-cycle effect latency between the link
port enable instruction and the DSP enabling the link port.
HLDCL
t
LCLKRWL
Min
1
3.5
t
4.0
4.0
8
LCLK
t
DLALC
Max
12
ADSP-21161N
Unit
ns
ns
ns
ns
ns
ns