ADSP-21161NKCAZ100 Analog Devices Inc, ADSP-21161NKCAZ100 Datasheet - Page 52

• Manufacturer Part Number: ADSP-21161NKCAZ100
• Description: IC,DSP,32-BIT,CMOS,BGA,225PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-21161NKCAZ100

• Rohs Compliant: YES
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 100MHz
• Non-volatile Memory: External
• On-chip Ram: 128kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.80V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 225-MBGA, 225-Mini-BGA
• Device Core Size: 32b
• Architecture: Enhanced Harvard
• Format: Floating Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 128KB
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (min): 1.71/3.13V
• Operating Supply Voltage (max): 1.89/3.47V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADSP21161NKCAZ100

ADSP-21161N
Table 37. SPI Interface Protocol — Slave Switching and Timing
1
2
Parameter
Timing Requirements
t
t
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
t
t
When CPHASE = 0 and baud rate is greater than 1, t
Applies to the first deassertion of SPIDS only.
SPICLKS
SPICHS
SPICLS
SDSCO
HDS
SSPIDS
HSPIDS
SDPPW
DSOE
DSDHI
DDSPIDS
HDSPIDS
HDLSBS
DSOV
2
1
1
Serial Clock Cycle
Serial Clock High Period
Serial Clock Low Period
SPIDS Assertion to First SPICLK Edge
CPHASE = 0
CPHASE = 1
Last SPICLK Edge to SPIDS Not Asserted
CPHASE = 0
Data Input Valid to SPICLK Edge (Data Input Set-up Time)
SPICLK Last Sampling Edge to Data Input Not Valid
SPIDS Deassertion Pulsewidth (CPHASE = 0)
SPIDS Assertion to Data Out Active
SPIDS Deassertion to Data High Impedance
SPICLK Edge to Data Out Valid (Data Out Delay Time)
SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
SPICLK Edge to Last Bit Out Not Valid
(Data Out Hold Time) for LSB
SPIDS Assertion to Data Out Valid (CPHASE = 0)
HDLSBS
affects the length of the last bit transmitted.
Rev. B | Page 52 of 60 | November 2009
0.5t
Min
8t
4t
4t
3.5t
1.5t
0
0
t
t
2
1.5
0.25t
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
SPICLK
+1
CCLK
–4
–4
+8
+8
+4.5t
+3
CCLK
Max
0.5t
0.5t
0.75t
1.5t
CCLK
CCLK
CCLK
CCLK
+5.5
+5.5
+7
+3
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns