ADSP-21161NKCAZ100 Analog Devices Inc, ADSP-21161NKCAZ100 Datasheet - Page 54

• Manufacturer Part Number: ADSP-21161NKCAZ100
• Description: IC,DSP,32-BIT,CMOS,BGA,225PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-21161NKCAZ100

• Rohs Compliant: YES
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 100MHz
• Non-volatile Memory: External
• On-chip Ram: 128kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.80V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 225-MBGA, 225-Mini-BGA
• Device Core Size: 32b
• Architecture: Enhanced Harvard
• Format: Floating Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 128KB
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (min): 1.71/3.13V
• Operating Supply Voltage (max): 1.89/3.47V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADSP21161NKCAZ100

ADSP-21161N
JTAG Test Access Port and Emulation
Table 38. JTAG Test Access Port and Emulation
1
2
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Characteristics
t
t
System Inputs = DATA47–16, ADDR23–0, RD, WR, ACK, RPBA, SPIDS, EBOOT, LBOOT, DMAR2–1, CLK_CFG1–0, CLKDBL, CS, HBR, SBTS, ID2–0, IRQ2–0, RESET,
System Outputs = BMS, MISO, MOSI, SPICLK, DxA, DxB, SCLKx, FSx, LxDAT7–0, LxCLK, LxACK, DATA47–16, SDWE, ACK, HBG, RAS, CAS, SDCLK1–0, SDCKE,
TCK
STAP
HTAP
SSYS
HSYS
TRSTW
DTDO
DSYS
BMS, MISO, MOSI, SPICLK, DxA, DxB, SCLKx, FSx, LxDAT7–0, LxCLK, LxACK, SDWE, HBG, RAS, CAS, SDCLK0, SDCKE, BRST, BR6–1, PA, MS3–0, FLAG11–0.
BRST, RD, WR, BR6–1, PA, MS3–0, ADDR23–0, FLAG11–0, DMAG2–1, DQM, REDY, CLKOUT, SDA10, TIMEXP, EMU, BMSTR, RSTOUT.
TCK Period
TDI, TMS Setup Before TCK High
TDI, TMS Hold After TCK High
System Inputs Setup Before TCK Low
System Inputs Hold After TCK Low
TRST Pulsewidth
TDO Delay from TCK Low
System Outputs Delay After TCK Low
TCK
TMS
TDO
SYSTEM
OUTPUTS
INPUTS
TDI
SYSTEM
t
DTDO
Figure 37. JTAG Test Access Port and Emulation
Rev. B | Page 54 of 60 | November 2009
1
t
1
2
TCK
t
DSYS
t
STAP
t
HTAP
t
SSYS
Min
t
5
6
2
15
4t
CK
CK
t
HSYS
Max
13
30
Unit
ns
ns
ns
ns
ns
ns
ns
ns