ADSP-21161NKCAZ100 Analog Devices Inc, ADSP-21161NKCAZ100 Datasheet - Page 43

• Manufacturer Part Number: ADSP-21161NKCAZ100
• Description: IC,DSP,32-BIT,CMOS,BGA,225PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-21161NKCAZ100

• Rohs Compliant: YES
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 100MHz
• Non-volatile Memory: External
• On-chip Ram: 128kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.80V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 225-MBGA, 225-Mini-BGA
• Device Core Size: 32b
• Architecture: Enhanced Harvard
• Format: Floating Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 128KB
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (min): 1.71/3.13V
• Operating Supply Voltage (max): 1.89/3.47V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADSP21161NKCAZ100

SDRAM Interface — Bus Master
Use these specifications for ADSP-21161N bus master accesses
of SDRAM:
Table 26. SDRAM Interface — Bus Master
1
2
3
4
5
SDRAM Interface — Bus Slave
These timing requirements allow a bus slave to sample the bus
master’s SDRAM command and detect when a refresh occurs:
Table 27. SDRAM Interface — Bus Slave
1
2
3
4
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
t
t
t
t
t
t
t
t
For the second, third, and fourth rising edges of SDCLK delay from CLKIN, add appropriate number of SDCLK period to the t
Subtract t
Command = SDCKE, MSx, DQM, RAS, CAS, SDA10, and SDWE.
SDRAM Controller adds one SDRAM CLK three-stated cycle delay on a read, followed by a write.
Valid when DSP transitions to SDRAM master from SDRAM slave.
Parameter
Timing Requirements
t
t
t
For the second, third, and fourth rising edges of SDCLK delay from CLKOUT, add appropriate number of SDCLK period to the t
SDCKR = 1 for SDCLK equal to core clock frequency and SDCKR = 2 for SDCLK equal to half core clock frequency.
Subtract t
Command = SDCKE, RAS, CAS, and SDWE.
SDSDK
HDSDK
DSDK1
SDK
SDKH
SDKL
DCADSDK
HCADSDK
SDTRSDK
SDENSDK
SDCTR
SDCEN
SDSDKTR
SDSDKEN
SDATR
SDAEN
value and the core clock to CLKIN ratio.
SSDKC1
SCSDK
HCSDK
SDCKR value and the Core clock to CLKOUT ratio.
CCLK
CCLK
from result if value is greater than or equal to t
from result if value is greater than or equal to t
Data Setup Before SDCLK
Data Hold After SDCLK
First SDCLK Rise Delay After CLKIN
SDCLK Period
SDCLK Width High
SDCLK Width Low
Command, Address, Data, Delay After SDCLK
Command, Address, Data, Hold After SDCLK
Data Three-State After SDCLK
Data Enable After SDCLK
Command Three-State After CLKIN
Command Enable After CLKIN
SDCLK Three-State After CLKIN
SDCLK Enable After CLKIN
Address Three-State After CLKIN
Address Enable After CLKIN
First SDCLK Rise after CLKOUT
Command Setup before SDCLK
Command Hold after SDCLK
5
4
1, 2
4
1, 2, 3
CCLK
CCLK
4
Rev. B | Page 43 of 60 | November 2009
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.
3
3
Min
2.0
2.3
0.75t
t
4
4
2.0
0.75t
0.5t
2
0
1
CCLK
0.25 t
0.4
Min
SDCK t
2
1
CCLK
CCLK
CCLK
CCLK
–1.5
+ 1.5
5
CCLK
100 MHz
0.5t
Max
0.75t
2 t
0.25t
0.5t
5
3
4
+7.2
0.5t
0.25t
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
+ 2.0
0.5
+ 6.0
+ 8.0
+2.5
Max
SDCKR t
Min
2.0
2.3
0.75t
t
3
3
2.0
0.75t
0.5t
2
0
1
CCLK
0.25 t
0.4
DSDK1
CCLK
CCLK
CCLK
DSDK1
CCLK
and t
–1.5
+ 1.5
CCLK
and t
SSDKC1
5
110 MHz
SSDKC1
0.25t
values, depending upon the SDCKR
ADSP-21161N
Max
0.75t
2 t
0.25t
0.5t
5
3
4
+7.2
0.5t
values, depending upon the
0.25t
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
+ 2.0
CCLK
+ 2.0
+ 6.0
+ 8.0
+2.5
Unit
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns