ADSP-21161NKCAZ100 Analog Devices Inc, ADSP-21161NKCAZ100 Datasheet - Page 4

• Manufacturer Part Number: ADSP-21161NKCAZ100
• Description: IC,DSP,32-BIT,CMOS,BGA,225PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-21161NKCAZ100

• Rohs Compliant: YES
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 100MHz
• Non-volatile Memory: External
• On-chip Ram: 128kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.80V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 225-MBGA, 225-Mini-BGA
• Device Core Size: 32b
• Architecture: Enhanced Harvard
• Format: Floating Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 128KB
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (min): 1.71/3.13V
• Operating Supply Voltage (max): 1.89/3.47V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADSP21161NKCAZ100

ADSP-21161N
When using the DAGs to transfer data in SIMD mode, two data
values are transferred with each access of memory or the regis-
ter file.
SIMD is supported only for internal memory accesses and is not
supported for off-chip accesses.
Independent, Parallel Computation Units
Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier, and shifter. These units perform single-cycle
instructions. The three units within each processing element are
arranged in parallel, maximizing computational throughput.
Single multifunction instructions execute parallel ALU and
multiplier operations. In SIMD mode, the parallel ALU and
multiplier operations occur in both processing elements. These
computation units support IEEE 32-bit single-precision float-
ing-point, 40-bit extended precision floating-point, and 32-bit
fixed-point data formats.
(HOST OR SLAVE)
COMPATIBLE
(OPTIONAL)
(OPTIONAL)
(OPTIONAL)
DEVICE
(OPTIONAL)
(OPTIONAL)
(OPTIONAL)
DEVICES
CLOCK
DEVICE
SPI
(2 MAX)
SERIAL
SERIAL
DEVICE
SERIAL
DEVICE
SERIAL
DEVICE
LINK
12
3
2
LBOOT
RPBA
LXCLK
LXDAT7-0
D0A
D0B
D1A
D1B
D2A
D2B
D3A
D3B
SPICLK
SPIDS
MOSI
MISO
RESET
CLKIN
XTAL
IRQ2-0
FLAG11-0
ID2-0
LXACK
SCLK0
FS0
SCLK1
FS1
SCLK2
FS2
SCLK3
FS3
CLK_CFG1-0
CLKDBL
EBOOT
TIMEXP
ADSP-21161N
RSTOUT
DATA47-16
ADDR23-0
SDCLK1-0
Rev. B | Page 4 of 60 | November 2009
DMAG2-1
DMAR2-1
CLKOUT
SDCKE
SDA10
MS3-0
SDWE
BR6-1
BRST
REDY
SBTS
JTAG
HBG
BMS
DQM
ACK
RAS
CAS
HBR
WR
Figure 2. System Diagram
RD
CS
PA
7
Data Register File
A general-purpose data register file is contained in each pro-
cessing element. The register files transfer data between the
computation units and the data buses, and store intermediate
results. These 10-port, 32-register (16 primary, 16 secondary)
register files, combined with the SHARC enhanced Harvard
architecture, allow unconstrained data flow between computa-
tion units and internal memory. The registers in PEX are
referred to as R0–R15 and in PEY as S0–S15.
Single-Cycle Fetch of Instruction and Four Operands
The ADSP-21161N features an enhanced Harvard architecture
in which the data memory (DM) bus transfers data and the pro-
gram memory (PM) bus transfers both instructions and data
(see
data memory buses and on-chip instruction cache, the proces-
sor can simultaneously fetch four operands (two over each data
bus) and an instruction (from the cache), all in a single cycle.
Figure
DATA
DATA
OE
WE
ACK
DATA
DATA
CS
ADDR
ADDR
CS
ADDR
2). With the ADSP-21161N’s separate program and
PERIPHERALS
(OPTIONAL)
DMA DEVICE
PROCESSOR
(OPTIONAL)
INTERFACE
(OPTIONAL)
(OPTIONAL)
MEMORY
EPROM
AND
HOST
BOOT
RAS
CAS
DQM
WE
CLK
CKE
A10
CS
ADDR
DATA
(OPTIONAL)
SDRAM