ADSP-21161NKCAZ100 Analog Devices Inc, ADSP-21161NKCAZ100 Datasheet - Page 48

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ADSP-21161NKCAZ100

Manufacturer Part Number
ADSP-21161NKCAZ100
Description
IC,DSP,32-BIT,CMOS,BGA,225PIN,PLASTIC
Manufacturer
Analog Devices Inc
Series
SHARC®r
Type
Fixed/Floating Pointr
Datasheet

Specifications of ADSP-21161NKCAZ100

Rohs Compliant
YES
Interface
Host Interface, Link Port, Serial Port
Clock Rate
100MHz
Non-volatile Memory
External
On-chip Ram
128kB
Voltage - I/o
3.30V
Voltage - Core
1.80V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
225-MBGA, 225-Mini-BGA
Device Core Size
32b
Architecture
Enhanced Harvard
Format
Floating Point
Clock Freq (max)
100MHz
Mips
100
Device Input Clock Speed
100MHz
Ram Size
128KB
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (min)
1.71/3.13V
Operating Supply Voltage (max)
1.89/3.47V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
225
Package Type
CSPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ADSP21161NKCAZ100

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ADSP-21161N
Table 34. Serial Ports —– Enable and Three-State
1
2
Table 35. Serial Ports — External Late Frame Sync
1
Parameter
Switching Characteristics
t
t
t
t
Parameter
Switching Characteristics
t
t
Referenced to drive edge.
SCLK/FS Configured as a transmit clock/frame sync with the DDIR bit = 1 in SPCTLx register.
MCE = 1, Transmit FS enable and Transmit FS valid follow t
DDTEN
DDTTE
DDTIN
DDTTI
DDTLFSE
DDTENFS
Data Delay from Late External Transmit FS or External Receive FS with
MCE = 1, MFD = 0
Data Enable from Late FS or MCE = 1, MFD = 0
Data Enable from External Transmit SCLK
Data Disable from External Transmit SCLK
Data Enable from Internal Transmit SCLK
Data Disable from Internal Transmit SCLK
1
DDTLFSE
Rev. B | Page 48 of 60 | November 2009
and t
DDTENFS
1
1, 2
1
1
1
.
Min
0.5
Min
4
0
Max
13
Max
10
3
Unit
ns
ns
Unit
ns
ns
ns
ns

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