ADSP-21161NKCAZ100 Analog Devices Inc, ADSP-21161NKCAZ100 Datasheet - Page 51

• Manufacturer Part Number: ADSP-21161NKCAZ100
• Description: IC,DSP,32-BIT,CMOS,BGA,225PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-21161NKCAZ100

• Rohs Compliant: YES
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 100MHz
• Non-volatile Memory: External
• On-chip Ram: 128kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.80V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 225-MBGA, 225-Mini-BGA
• Device Core Size: 32b
• Architecture: Enhanced Harvard
• Format: Floating Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 128KB
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (min): 1.71/3.13V
• Operating Supply Voltage (max): 1.89/3.47V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADSP21161NKCAZ100

SPI Interface Specifications
Table 36. SPI Interface Protocol — Master Switching and Timing
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
t
t
t
SSPIDM
HSPIDM
SPICLKM
SPICHM
SPICLM
DDSPIDM
HDSPIDM
SDSCIM_0
SDSCIM_1
HDSM
SPITDM
CPHASE = 1
CPHASE = 0
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
Data Input Valid to SPICLK Edge (Data Input Set-up Time) 0.5t
SPICLK Last Sampling Edge to Data Input Not Valid
Serial Clock Cycle
Serial Clock High Period
Serial Clock Low Period
SPICLK Edge to Data Out Valid (Data Out Delay Time)
SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 0
FLAG3–0 (SPI Device Select) Low to First SPICLK Edge for
CPHASE = 0
FLAG3–0 (SPI Device Select) Low to First SPICLK Edge for
CPHASE = 1
Last SPICLK Edge to FLAG3–0 High
FLAG3-0
Sequential Transfer Delay
SPICLK
(CP = 0)
SPICLK
(CP = 1)
MOSI
(INPUT)
MOSI
(INPUT)
MISO
MISO
t
S S P I D M
t
S D S C I M
VALID
MSB
Figure 35. SPI Interface Protocol — Master Switching and Timing
t
t
MSB
S P I C H M
S P I C L M
VALID
MSB
t
H S P I D M
t
t
D D S P I D M
t
S S P I D M
t
MSB
Rev. B | Page 51 of 60 | November 2009
S P I C L M
S P I C H M
t
D D S P I D M
t
H S P I D M
t
Min
0.5t
8t
4t
4t
5t
3t
t
2t
H D S P I D M
t
CCLK
t
S S P I D M
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
HDSPIDM
CCLK
CCLK
–3
t
VALID
S P I C L K M
–4
–4
LSB
+10
+1
100 MHz
LSB
VALID
LSB
Max
3
t
H D S M
LSB
t
H S P I D M
Min
0.5t
0.5t
8t
4t
4t
0
5t
3t
t
2t
CCLK
t
S P I T D M
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
–3
–4
–4
–4
+10
+1
110 MHz
ADSP-21161N
Max
3
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns