ADSP-21161NKCAZ100 Analog Devices Inc, ADSP-21161NKCAZ100 Datasheet - Page 9

• Manufacturer Part Number: ADSP-21161NKCAZ100
• Description: IC,DSP,32-BIT,CMOS,BGA,225PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-21161NKCAZ100

• Rohs Compliant: YES
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 100MHz
• Non-volatile Memory: External
• On-chip Ram: 128kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.80V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 225-MBGA, 225-Mini-BGA
• Device Core Size: 32b
• Architecture: Enhanced Harvard
• Format: Floating Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 128KB
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (min): 1.71/3.13V
• Operating Supply Voltage (max): 1.89/3.47V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADSP21161NKCAZ100

(for example 10k ohm). These pins must be driven low with a
strong enough drive strength (10–50 ohms) to overcome the
SHARC keeper latches present on these pins. If the drive
strength provided is not strong enough, data access failures can
occur.
For single processor SHARC systems using this host access fea-
ture, address pins ADDR17, ADDR18, ADDR19, and ADDR20
may be tied low (for example through a 10k ohm resistor),
driven low by a buffer/driver, or left floating. Any of these
options is sufficient.
General-Purpose I/O Ports
The ADSP-21161N also contains 12 programmable, general
purpose I/O pins that can function as either input or output. As
output, these pins can signal peripheral devices; as input, these
pins can provide the test for conditional branching.
Program Booting
The internal memory of the ADSP-21161N can be booted at
system power-up from either an 8-bit EPROM, a host processor,
the SPI interface, or through one of the link ports. Selection of
the boot source is controlled by the Boot Memory Select (BMS),
EBOOT (EPROM Boot), and Link/Host Boot (LBOOT) pins.
8-, 16-, or 32-bit host processors can also be used for booting.
Phase-Locked Loop and Crystal Double Enable
The ADSP-21161N uses an on-chip phase-locked loop (PLL) to
generate the internal clock for the core. The CLK_CFG1–0 pins
are used to select ratios of 2:1, 3:1, and 4:1. In addition to the
PLL ratios, the CLKDBL pin can be used for more clock ratio
options. The (1 /2 CLKIN) rate set by the CLKDBL
pin determines the rate of the PLL input clock and the rate at
which the external port operates. With the combination of
CLK_CFG1–0 and CLKDBL, ratios of 2:1, 3:1, 4:1, 6:1, and 8:1
between the core and CLKIN are supported. See also
on Page
Power Supplies
The ADSP-21161N has separate power supply connections for
the analog (AV
(V
meet the 1.8 V requirement. The external supply must meet the
3.3 V requirement. All external supply pins must be connected
to the same supply.
Note that the analog supply (AV
clock generator PLL. To produce a stable clock, provide an
external circuit to filter the power input to the AV
the filter as close as possible to the pin. The AV
shown in
multiprocessor system. To prevent noise coupling, use a wide
trace for the analog ground (AGND) signal and install a decou-
pling capacitor as close as possible to the pin.
DDEXT
) power supplies. The internal and analog supplies must
21.
Figure 6
DD
/AGND), internal (V
must be added for each ADSP-21161N in the
DD
) powers the ADSP-21161N’s
DDINT
), and external
DD
DD
filter circuit
Rev. B | Page 9 of 60 | November 2009
pin. Place
Figure 12
DEVELOPMENT TOOLS
The ADSP-21161N is supported with a complete set of software
and hardware development tools, including Analog Devices
emulators and VisualDSP++
same emulator hardware that supports other SHARC DSPs, also
fully emulates the ADSP-21161N.
The VisualDSP++ project management environment lets pro-
grammers develop and debug an application. This environment
includes an easy-to-use assembler that is based on an algebraic
syntax; an archiver (librarian/library builder), a linker, a loader,
a cycle-accurate instruction-level simulator, a C/C++ compiler,
and a C/C++ run-time library that includes DSP and mathemat-
ical functions. Two key points for these tools are:
Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can:
The VisualDSP++ IDE lets programmers define and manage
DSP software development. Its dialog boxes and property pages
let programmers configure and manage all of the SHARC devel-
opment tools, including the syntax highlighting in the
VisualDSP++ editor. This capability permits:
Analog Devices DSP emulators use the IEEE 1149.1 JTAG test
access port of the ADSP-21161N processor to monitor and con-
trol the target board processor during emulation. The emulator
• Compiled ADSP-21161N C/C++ code efficiency—The
• ADSP-2106x family code compatibility—The assembler
• View mixed C/C++ and assembly code (interleaved source
• Insert break points
• Set conditional breakpoints on registers, memory, and
• Trace instruction execution
• Perform linear or statistical profiling of program execution
• Fill, dump, and graphically plot the contents of memory
• Source level debugging
• Create custom debugger windows
• Controlling how the development tools process inputs and
• Maintaining a one-to-one correspondence with the tool’s
compiler has been developed for efficient translation of
C/C++ code to ADSP-21161N assembly. The DSP has
architectural features that improve the efficiency of
compiled C/C++ code.
has legacy features to ease the conversion of existing
ADSP-2106x applications to the ADSP-21161N.
and object information)
stacks
generate outputs.
command line switches.
V
DDINT
Figure 6. Analog Power (AV
10
0.1 F
®
development environment. The
AGND
DD
) Filter Circuit
ADSP-21161N
0.01 F
AV
DD