ADSP-21161NKCAZ100 Analog Devices Inc, ADSP-21161NKCAZ100 Datasheet - Page 24

• Manufacturer Part Number: ADSP-21161NKCAZ100
• Description: IC,DSP,32-BIT,CMOS,BGA,225PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-21161NKCAZ100

• Rohs Compliant: YES
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 100MHz
• Non-volatile Memory: External
• On-chip Ram: 128kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.80V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 225-MBGA, 225-Mini-BGA
• Device Core Size: 32b
• Architecture: Enhanced Harvard
• Format: Floating Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 128KB
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (min): 1.71/3.13V
• Operating Supply Voltage (max): 1.89/3.47V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADSP21161NKCAZ100

ADSP-21161N
Clock Input
In systems that use multiprocessing or SBSRAM, CLKDBL can-
not be enabled nor can the systems use an external crystal as the
CLKIN source.
Table 11. Clock Input
1
Parameter
Timing Requirements
t
t
t
t
t
Switching Characteristics
t
t
t
t
CLKIN is dependent on the configuration of the CLKCFGx and CLKDBL pins to achieve desired t
CK
CKL
CKH
CKRF
CCLK
DCKOO
CKOP
CKWH
CKWL
CLKIN Period
1
CLKIN Width Low
CLKIN Width High
CLKIN Rise/Fall (0.4 V–2.0 V)
CCLK Period
CLKOUT Delay After CLKIN
CLKOUT Period
CLKOUT Width High
CLKOUT Width Low
1
1
CLKIN
CLKOUT
CLKOUT
NOTES:
1. WHEN CLKDBL IS DISABLED, ANY SPECIFICATION TO CLKIN
2. WHEN CLKDBL IS ENABLED, ANY SPECIFICATION TO CLKIN
APPLIES TO THE RISING EDGE, ONLY.
APPLIES TO THE RISING OR FALLING EDGE.
t
t
DCKOO
DCKOO
Min
20
7.5
7.5
10
0
t
t
t
Rev. B | Page 24 of 60 | November 2009
CK
CKOP
CKOP
1
2
t
CKWH
–1
/2–2
/2–2
2
Figure 15. Clock Input
t
CKH
t
t
CKWH
CKOP
t
DCKOO
100 MHz
2
1
2
Max
238
119
119
3
30
2
t
t
t
CK
CKOP
CKOP
t
+1
CKOP
t
/2+2
/2+2
CK
t
CKWL
Do not use CLKOUT as the clock source for the SBSRAM
device. Using an external crystal in conjunction with CLKDBL
to generate a CLKOUT frequency is not supported. Negative
hold times can result from the potential skew between CLKIN
and CLKOUT.
t
1
CKL
t
2
CKWL
CCLK
1
.
Min
18
7
7
9
0
t
t
t
CK
CKOP
CKOP
–1
/2–2
/2–2
110 MHz
Max
238
119
119
3
30
2
t
t
t
CK
CKOP
CKOP
+1
/2+2
/2+2
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns