ADSP-21161NKCAZ100 Analog Devices Inc, ADSP-21161NKCAZ100 Datasheet - Page 19

• Manufacturer Part Number: ADSP-21161NKCAZ100
• Description: IC,DSP,32-BIT,CMOS,BGA,225PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-21161NKCAZ100

• Rohs Compliant: YES
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 100MHz
• Non-volatile Memory: External
• On-chip Ram: 128kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.80V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 225-MBGA, 225-Mini-BGA
• Device Core Size: 32b
• Architecture: Enhanced Harvard
• Format: Floating Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 128KB
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (min): 1.71/3.13V
• Operating Supply Voltage (max): 1.89/3.47V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADSP21161NKCAZ100

ELECTRICAL CHARACTERISTICS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Parameter Description
V
V
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
AI
C
See
Applies to input pins: DATA47–16, ADDR23–0, MS3–0, SBTS, IRQ2–0, FLAG11–0, HBG, HBR, CS, BR6–1, ID2–0, RPBA, BRST, FSx, DxA, DxB, SCLKx, RAS, CAS, SDWE,
Applies to input pins with 20 k internal pull-ups: RD, WR, ACK, DMAR1, DMAR2, PA, TRST, TMS, TDI.
Applies to CLKIN only.
Applies to all pins with keeper latches: ADDR23–0, DATA47–0, MS3–0, BRST, CLKOUT.
Current required to switch from kept high to low or from kept low to high.
Characterized, but not tested.
Applies to three-statable pins: DATA47–16, ADDR23–0, MS3–0, CLKOUT, FLAG11–0, REDY, HBG, BMS, BR6–1, RAS, CAS, SDWE, DQM, SDCLKx, SDCKE, SDA10,
Applies to three-statable pins with 20 k pull-ups: RD, WR, DMAG1, DMAG2, PA.
Applies to three-statable pins with 50 k internal pull-ups: DxA, DxB, SCLKx, SPICLK., EMU, MISO, MOSI.
Applies to three-statable pins with 50 k internal pull-downs: LxDAT7–0 (below Revision1.2), LxCLK, LxACK. Use I
Applies to three-statable pins with 20 k internal pull-downs: LxDAT7-0 (Revision 1.2 and higher).
The test program used to measure I
Current numbers are for V
I
I
Idle denotes ADSP-21161N state during execution of IDLE instruction.
Characterized, but not tested.
Applies to all signal pins.
Guaranteed, but not tested.
IH
IL
IHC
ILC
IKH
IKL
IKH-OD
IKL-OD
ILPU
OZH
OZL
OZLPU1
OZLPU2
OZHPD1
OZHPD2
DD-INPEAK
DD-INHIGH
DD-INLOW
DD-IDLE
Applies to output and bidirectional pins: DATA47–16, ADDR23–0, MS3–0, RD, WR, ACK, DQM, FLAG11–0, HBG, REDY, DMAG1, DMAG2,
BR6–1, BMSTR, PA, BRST, FSx, DxA, DxB, SCLKx, RAS, CAS, SDWE, SDA10, LxDAT7–0, LxCLK, LxACK, SPICLK, MOSI, MISO, BMS, SDCLKx, SDCKE, EMU, XTAL,
TDO, CLKOUT, TIMEXP, RSTOUT.
SDCLK0, LxDAT7–0, LxCLK, LxACK, SPICLK, MOSI, MISO, SPIDS, EBOOT, LBOOT, BMS, SDCKE, CLK_CFGx, CLKDBL, TCK, RESET, CLKIN.
BRST.
measurements made using typical applications are less than specified.
DDINHIGH
DDINLOW
OH
OL
IN
DD
Output Drive Currents on Page 55
is a composite average based on a range of low activity code.
is a composite average based on a range of high activity code.
High Level Output Voltage
Low Level Output Voltage
High Level Input Current
Low Level Input Current
CLKIN High Level Input Current
CLKIN Low Level Input Current
Keeper High Load Current
Keeper Low Load Current
Keeper High Overdrive Current
Keeper Low Overdrive Current
Low Level Input Current Pull-Up
Three-State Leakage Current
Three-State Leakage Current
Three-State Leakage Current Pull-Up1
Three-State Leakage Current Pull-Up2
Three-State Leakage Current Pull-Down1
Three-State Leakage Current Pull-Down2
Supply Current (Internal)
Supply Current (Internal)
Supply Current (Internal)
Supply Current (Idle)
Supply Current (Analog)
Input Capacitance
DDINT
and AVDD supplies combined.
DDINPEAK
20, 21
for typical drive current capabilities.
15, 18
represents worst-case processor operation and is not sustainable under normal application conditions. Actual internal power
3
19
3, 4
14, 15
15, 16
15, 17
6
1
6
1
9, 10, 11
9, 12, 13
6, 7, 8
5
6, 7, 8
5
4
Rev. B | Page 19 of 60 | November 2009
10
11
12
13
For more information, see Power Dissipation on Page 21.
For more information, see Power Dissipation on Page 21.
For more information, see Power Dissipation on Page 21.
For more information, see Power Dissipation on Page 21.
Test Conditions
@ V
@ V
@ V
@ V
@ V
@ V
@ V
@ V
@ V
@ V
@ V
@ V
@ V
@ V
@ V
@ V
@ V
t
t
t
t
t
t
t
t
@ AV
f
IN
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
= 1 MHz, T
DDEXT
DDEXT
DDEXT
DDEXT
DDEXT
DDEXT
DDEXT
DDEXT
DDEXT
DDEXT
DDEXT
DDEXT
DDEXT
DDEXT
DDEXT
DDEXT
DDEXT
= 9.0 ns, V
= 10.0 ns, V
= 9.0 ns, V
= 10.0 ns, V
= 9.0 ns, V
= 10.0 ns, V
= 9.0 ns, V
= 10.0 ns, V
DD
= Max
= Max, V
= Min, I
= Min, I
= Max, V
= Max, V
= Max, V
= Max, V
= Max, V
= Max, V
= Max
= Max
= Max, V
= Max, V
= Max, V
= Max, V
= Max, V
= Max, V
CASE
DDINT
DDINT
DDINT
DDINT
OH
OL
DDINT
DDINT
DDINT
DDINT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
= 25°C, V
= 4.0 mA
= –2.0 mA
= V
= V
= 0 V
= V
= 0 V
= 2.0 V
= 0.8 V
= 0 V
= 0 V
= 0 V
= 0 V
= V
= V
= Max
= Max
= Max
= Max
= Max
= Max
= Max
= Max
DDEXT
DDEXT
DDEXT
DDEXT
DDEXT
IN
Max
2
Max
Max
Max
Max
= 1.8 V
2
OZHPD2
for Rev. 1.2 and higher.
Min
2.4
–300
300
–250
50
ADSP-21161N
Max
0.4
10
10
35
35
–100
200
350
10
10
500
350
350
500
965
900
700
650
535
500
425
400
10
4.7
Unit
V
V
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
mA
mA
mA
mA
mA
pF