ADSP-21161NKCAZ100 Analog Devices Inc, ADSP-21161NKCAZ100 Datasheet - Page 46

• Manufacturer Part Number: ADSP-21161NKCAZ100
• Description: IC,DSP,32-BIT,CMOS,BGA,225PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-21161NKCAZ100

• Rohs Compliant: YES
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 100MHz
• Non-volatile Memory: External
• On-chip Ram: 128kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.80V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 225-MBGA, 225-Mini-BGA
• Device Core Size: 32b
• Architecture: Enhanced Harvard
• Format: Floating Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 128KB
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (min): 1.71/3.13V
• Operating Supply Voltage (max): 1.89/3.47V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADSP21161NKCAZ100

ADSP-21161N
Table 29. Link Ports — Transmit
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
SLACH
HLACH
DLDCH
HLDCH
LCLKTWL
LCLKTWH
DLACLK
LDAT7-0
LCLK
LACK (IN)
TRANSMIT
t
HLDCH
LACK Setup Before LCLK High
LACK Hold After LCLK High
Data Delay After LCLK High
Data Hold After LCLK High
LCLK Width Low
LCLK Width High
LCLK Low Delay After LACK High
THE
OUT
t
t
SLACH
LCLKTWH
t
DLDCH
REQUIREMENT APPLIES TO THE RISING EDGE OF LCLK ONLY FOR THE FIRST NIBBLE TRANSMITTED.
t
LCLKTWL
Rev. B | Page 46 of 60 | November 2009
LAST NIBBLE/BYTE
TRANSMITTED
Figure 32. Link Ports—Transmit
t
SLACH
FIRST NIBBLE/BYTE
TRANSMITTED
t
HLACH
Min
8
–2
0
0.5t
0.5t
0.5t
LCLK
LCLK
LCLK
–1.0
–1.0
+3
LCLK INACTIVE
(HIGH)
Max
3
0.5t
0.5t
3t
LCLK
LCLK
LCLK
+11
+1.0
+1.0
t
DLACLK
Unit
ns
ns
ns
ns
ns
ns
ns