ADSP-21161NKCAZ100 Analog Devices Inc, ADSP-21161NKCAZ100 Datasheet - Page 41

• Manufacturer Part Number: ADSP-21161NKCAZ100
• Description: IC,DSP,32-BIT,CMOS,BGA,225PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-21161NKCAZ100

• Rohs Compliant: YES
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 100MHz
• Non-volatile Memory: External
• On-chip Ram: 128kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.80V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 225-MBGA, 225-Mini-BGA
• Device Core Size: 32b
• Architecture: Enhanced Harvard
• Format: Floating Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 128KB
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (min): 1.71/3.13V
• Operating Supply Voltage (max): 1.89/3.47V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADSP21161NKCAZ100

DMA Handshake
These specifications describe the three DMA handshake modes.
In all three modes DMAR is used to initiate transfers. For hand-
shake mode, DMAG controls the latching or enabling of data
externally. For external handshake mode, the data transfer is
controlled by the ADDR23–0, RD, WR, MS3–0, ACK, and
Table 25. DMA Handshake
1
2
3
4
5
6
7
Parameter
Timing Requirements
t
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
W = (number of wait states specified in WAIT register) t
HI = t
Only required for recognition in the current cycle.
Maximum throughput (@ 110 MHz) using DMARx/DMAGx handshaking equals t
t
Use t
t
See
This parameter applies for synchronous access mode only.
SDATDGL
VDATDGH
SDRC
WDR
SDATDGL
HDATIDG
DATDRH
DMARLL
DMARH
DDGL
WDGH
WDGL
HDGC
VDATDGH
DATRDGH
DGWRL
DGWRH
DGWRR
DGRDL
DRDGH
DGRDR
DGWR
DADGH
DDGHA
to non-synchronous access mode only.
be driven t
n equals the number of extra cycles that the access is prolonged.
Example System Hold Time Calculation on Page 55
DMARLL
CKOP
is the data setup requirement if DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of the write, the data can
is valid if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then t
(if data bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
DATDRH
if DMARx transitions synchronous with CLKIN. Otherwise, use t
DMARx Setup Before CLKIN
DMARx Width Low
(Nonsynchronous)
Data Setup After DMAGx Low
Data Hold After DMAGx High
Data Valid After DMARx High
DMARx Low Edge to Low Edge
DMARx Width High
DMAGx Low Delay After CLKIN
DMAGx High Width
DMAGx Low Width
DMAGx High Delay After CLKIN
Data Valid Before DMAGx High
Data Disable After DMAGx High
WRx Low Before DMAGx Low
DMAGx Low Before WRx High
WRx High Before DMAGx High
RDx Low Before DMAGx Low
RDx Low Before DMAGx High
RDx High Before DMAGx High
DMAGx High to WRx, RDx Low
Address/Select Valid to DMAGx High 15
Address/Select Hold After DMAGx
High
after DMARx is brought high.
2
2
1
3
3
7
7
4
5
6
for calculation of hold times given capacitive and dc loads.
Min
3.5
t
2
t
t
0.25t
0.5t
t
t
t
0.25t
–1.5
t
–1.5
–1.5
t
–1.5
0.5t
1
Rev. B | Page 41 of 60 | November 2009
CCLK
CKOP
CCLK
CKOP
CKOP
CKOP
CKOP
CKOP
CCLK
CCLK
+4.5
+4.5
– 0.5t
– 0.25t
– 0.25t
– 0.5t
– 0.5t
CCLK
CCLK
– 1+HI
– 2+HI
CKOP
+1
– 3
CCLK
CCLK
CCLK
.
CCLK
CCLK
WDR
–2+W
– 1
– 2 +W
+1.0
– 8
100 MHz
and t
WDR
DMARH
+ t
Max
t
t
0.25t
t
t
0.25t
+2
+2
+2
+2
CKOP
CKOP
CKOP
CKOP
DMARH
DMAG signals. For Paced Master mode, the data transfer is
controlled by ADDR23–0, RD, WR, MS3–0, and ACK (not
DMAG). For Paced Master mode, the Memory Read-Bus Mas-
ter, Memory Write-Bus Master, and Synchronous Read/Write-
Bus Master timing specifications for ADDR23–0, RD, WR,
MS3–0, DATA47–16, and ACK also apply.
.
+3
– 0.5t
– 0.25t
– 0.25t
CCLK
CCLK
= (t
+9
+4
CCLK
CCLK
CCLK
CCLK
+4.5) + (t
–7
+9 t
+5 t
Min
3.5
t
2
t
t
0.25t
0.5t
t
0.25t
–1.5
t
–1.5
–1.5
t
–1.5
0.5t
13
1
CCLK
CKOP
CCLK
CKOP
CKOP
CKOP
CKOP
CKOP
CCLK
CCLK
CCLK
+4.5
+4.5
+4.5)= 27 ns (37 MHz). This throughput limit applies
– 0.5t
– 0.25t
– 0.25t
– 0.5t
– 0.5t
CCLK
CCLK
VDATDGH
– 1+HI
– 2+HI
+1
– 3
CCLK
CCLK
CCLK
CCLK
CCLK
–2+W
– 1
– 2 +W
= t
+1.0
– 8
110 MHz
CKOP
– 0.25t
Max
t
t
0.25t
t
t
0.25t
+2
+2
+2
+2
CKOP
CKOP
CKOP
CKOP
ADSP-21161N
CCLK
+3
– 0.5t
– 0.25t
– 0.25t
CCLK
CCLK
– 8 + (n × t
+9
+4
CCLK
CCLK
CCLK
–7
+9 ns
+5 ns
CKOP
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
) where