ADSP-21161NKCAZ100 Analog Devices Inc, ADSP-21161NKCAZ100 Datasheet - Page 32

• Manufacturer Part Number: ADSP-21161NKCAZ100
• Description: IC,DSP,32-BIT,CMOS,BGA,225PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-21161NKCAZ100

• Rohs Compliant: YES
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 100MHz
• Non-volatile Memory: External
• On-chip Ram: 128kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.80V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 225-MBGA, 225-Mini-BGA
• Device Core Size: 32b
• Architecture: Enhanced Harvard
• Format: Floating Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 128KB
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (min): 1.71/3.13V
• Operating Supply Voltage (max): 1.89/3.47V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADSP21161NKCAZ100

ADSP-21161N
Synchronous Read/Write — Bus Master
Use these specifications for interfacing to external memory sys-
tems that require CLKIN, relative to timing or for accessing a
slave ADSP-21161N (in multiprocessor memory space). When
accessing a slave ADSP-21161N, these switching characteristics
Table 18. Synchronous Read/Write — Bus Master
Parameter
Timing Requirements
t
t
t
t
Switching Characteristics
t
t
t
t
t
t
t
SSDATI
HSDATI
SACKC
HACKC
DADDO
HADDO
DRDO
DWRO
DRWL
DDATO
HDATO
WRITE CYCLE
READ CYCLE
ACK
RD
DATA
WR
DATA (OUT)
CLKIN
MSx,
(IN)
ADDRESS
(IN)
BRST
Data Setup Before CLKIN
Data Hold After CLKIN
ACK Setup Before CLKIN
ACK Hold After CLKIN
Address, MSx, BMS, BRST, Delay After CLKIN
Address, MSx, BMS, BRST, Hold After CLKIN
RD High Delay After CLKIN
WR High Delay After CLKIN
RD/WR Low Delay After CLKIN
Data Delay After CLKIN
Data Hold After CLKIN
t
t
DRWL
DRWL
t
DDATO
t
DADDO
Figure 23. Synchronous Read/Write — Bus Master
Rev. B | Page 32 of 60 | November 2009
must meet the slave's timing requirements for synchronous
read/writes (see
Page
master) timing requirements for data and acknowledge setup
and hold times.
33). The slave ADSP-21161N must also meet these (bus
t
SACKC
Min
5.5
1
0.5t
1
1.5
0.25t
0.25t
0.25t
1.5
CCLK
CCLK
CCLK
CCLK
t
SSDATI
t
+3
HADDO
–1
–1
–1
Synchronous Read/Write — Bus Slave on
t
t
DRDO
DWRO
Max
10
0.25t
0.25t
0.25t
12.5
t
HACKC
t
t
HSDATI
HDATO
CCLK
CCLK
CCLK
+9
+9
+9
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns