ADSP-21161NKCAZ100 Analog Devices Inc, ADSP-21161NKCAZ100 Datasheet - Page 39

• Manufacturer Part Number: ADSP-21161NKCAZ100
• Description: IC,DSP,32-BIT,CMOS,BGA,225PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-21161NKCAZ100

• Rohs Compliant: YES
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 100MHz
• Non-volatile Memory: External
• On-chip Ram: 128kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.80V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 225-MBGA, 225-Mini-BGA
• Device Core Size: 32b
• Architecture: Enhanced Harvard
• Format: Floating Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 128KB
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (min): 1.71/3.13V
• Operating Supply Voltage (max): 1.89/3.47V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADSP21161NKCAZ100

Three-State Timing — Bus Master, Bus Slave
These specifications show how the memory interface is disabled
(stops driving) or enabled (resumes driving) relative to CLKIN
and the SBTS pin. This timing is applicable to bus master transi-
tion cycles (BTC) and host transition cycles (HTC) as well as the
SBTS pin.
Table 24. Three-State Timing — Bus Master, Bus Slave
1
2
3
4
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Strobes = RD, WR, DMAGx.
Where N = 0.5, 1.0, 1.5 for 1:2, 1:3, and 1:4, respectively.
In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write.
Memory Interface = Address, RD, WR, MSx, DMAGx, and BMS (in EPROM boot mode). BMS is only an output in EPROM boot mode.
STSCK
HTSCK
MIENA
MIENS
MIENHG
MITRA
MITRS
MITRHG
DATEN
DATTR
ACKEN
ACKTR
CDCEN
CDCTR
ATRHBG
STRHBG
BTRHBG
MENHBG
SBTS Setup Before CLKIN
SBTS Hold After CLKIN
Address/Select Enable After CLKIN High
Strobes Enable After CLKIN High
HBG Enable After CLKIN
Address/Select Disable After CLKIN High
Strobes Disable After CLKIN High
HBG Disable After CLKIN
Data Enable After CLKIN
Data Disable After CLKIN
ACK Enable After CLKIN High
ACK Disable After CLKIN High
CLKOUT Enable After CLKIN
CLKOUT Disable After CLKIN
Address/Select Disable Before HBG Low
RD/WR/DMAGx Disable Before HBG Low
BMS Disable Before HBG Low
Memory Interface Enable After HBG High
3
2
3
2
4
1
Rev. B | Page 39 of 60 | November 2009
4
4
4
1.5
Min
6
2
1.5
0.5t
t
0.5t
1.5
1.5
1.5
0.2
0.5t
t
1.5t
t
0.5t
t
CKOP
CKOP
CKOP
CKOP
1.5
During reset, the DSP will not respond to SBTS, HBR, and MMS
accesses. Although the DSP will recognize HBR asserted before
reset, a HBG will not be returned by the DSP until after reset is
deasserted and the DSP completes bus synchronization.
CKOP
CKOP
CKOP
CKOP
CKOP
–
+
–5
–
+N t
+N t
–6
–4
t
t
CCLK
CCLK
CCLK
CCLK
17
4
–
9
Max
+9
9
0.5t
t
0.5t
10
6
9
5
0.5t
t
1.5t
t
0.5t
t
CKOP
CKOP
CKOP
CKOP
CKOP
CKOP
CKOP
CKOP
CKOP
–
+
+5
–
+N t
+N t
+2
+2
t
t
CCLK
CCLK
CCLK
CCLK
+3
12.5
–
+5
ADSP-21161N
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns