ADSP-21161NKCAZ100 Analog Devices Inc, ADSP-21161NKCAZ100 Datasheet - Page 23

• Manufacturer Part Number: ADSP-21161NKCAZ100
• Description: IC,DSP,32-BIT,CMOS,BGA,225PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-21161NKCAZ100

• Rohs Compliant: YES
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 100MHz
• Non-volatile Memory: External
• On-chip Ram: 128kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.80V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 225-MBGA, 225-Mini-BGA
• Device Core Size: 32b
• Architecture: Enhanced Harvard
• Format: Floating Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 128KB
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (min): 1.71/3.13V
• Operating Supply Voltage (max): 1.89/3.47V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADSP21161NKCAZ100

Power-Up Sequencing — Silicon Revision 1.2 and Greater
The timing requirements for DSP startup are given in
During the power-up sequence of the DSP, differences in the
ramp-up rates and activation time between the two supplies can
cause current to flow in the I/O ESD protection circuitry. To
prevent damage to the ESD diode protection circuitry, Analog
Devices recommends including a bootstrap Schottky diode.
The bootstrap Schottky diode is connected between the 1.8 V
and 3.3 V power supplies as shown in
ADSP-21161N from partially powering the 3.3 V supply.
Including a Schottky diode will shorten the delay between
the supply ramps and thus prevent damage to the ESD diode
Table 10. Power-Up Sequencing Silicon Revision 1.2 and Greater (DSP Startup)
1
2
3
4
5
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Requirements
t
Valid V
Assumes a stable CLKIN signal, after meeting worst-case start-up timing of crystal oscillators. Refer to the crystal oscillator manufacturer's data sheet for start-up time.
Based on CLKIN cycles.
Applies after the power-up sequence is complete. Subsequent resets require a minimum of 4 CLKIN cycles for RESET to be held low in order to properly initialize and
The 4080 cycle count depends on t
RSTVDD
IVDDEVDD
CLKVDD
CLKRST
PLLRST
WRST
CORERST
depending on the design of the power supply subsystem.
Assume a 25 ms maximum oscillator start-up time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.
propagate default states at all I/O pins.
4081 cycles maximum.
DDINT
/V
DDEXT
RESET Low Before V
V
CLKIN Valid After V
CLKIN Valid Before RESET Deasserted
PLL Control Setup Before RESET Deasserted
Subsequent RESET Low Pulsewidth
DSP core reset deasserted after RESET deasserted
assumes that the supplies are fully ramped to their 1.8 and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds
DDINT
VDDINT
VDDEXT
CLKIN
CLKDBL
CLK_CFG1-0
RSTOUT
on Before V
RESET
SRST
specification in
Figure 14. Power-Up Sequencing for Silicon Revision 1.2 and Greater (DSP Startup)
DDEXT
DDINT
DDINT
t
Figure
RSTVDD
/V
/V
DDEXT
DDEXT
t
IVDDEVDD
Table
13. It protects the
Valid
on
t
12. If setup time is not met, one additional CLKIN cycle may be added to the core reset time, resulting in
CLKVDD
Rev. B | Page 23 of 60 | November 2009
1
4
2
Table
3
10.
t
PLLRST
t
CLKRST
protection circuitry. With this technique, if the 1.8 V rail rises
ahead of the 3.3 V rail, the Schottky diode pulls the 3.3 V rail
along with the 1.8 V rail.
DC INPUT
SOURCE
t
CORERST
Min
0
–50
0
10
20
4t
4080t
Figure 13. Dual Voltage Schottky Diode
REGULATOR
REGULATOR
1.8V CORE
VOLTAGE
VOLTAGE
CK
3.3V I/O
CK
3, 5
Max
+200
200
ADSP-21161N
V
V
DDEXT
DDINT
ADSP-21161N
Unit
ns
ms
μs
μs
ns
ms