ADSP-21160NCB-100 Analog Devices Inc, ADSP-21160NCB-100 Datasheet - Page 18

• Manufacturer Part Number: ADSP-21160NCB-100
• Description: IC,DSP,32-BIT,CMOS,BGA,400PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21160NCB-100

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 100MHz
• Non-volatile Memory: External
• On-chip Ram: 512kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.90V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Package: 400BGA
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 100 MHz
• Ram Size: 512 KB
• Device Million Instructions Per Second: 100 MIPS

ADSP-21160N
Clock Input
For Clock Input, see
Table 5. Clock Input
Reset
For Reset, see
Table 6. Reset
1
2
Parameter
Timing Requirements
t
t
t
t
t
Parameter
Timing Requirements
t
t
Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 µs while RESET is
Only required if multiple ADSP-21160Ns must come out of reset synchronous to CLKIN with program counters (PC) equal. Not required for multiple
CK
CKL
CKH
CKRF
CCLK
WRST
SRST
low, assuming stable V
ADSP-21160Ns communicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes itself
after reset.
Table 6
CLKIN Period
CLKIN Width Low
CLKIN Width High
CLKIN Rise/Fall (0.4 V–2.0 V)
Core Clock Period
RESET Pulsewidth Low
RESET Setup Before CLKIN High
Table 5
DD
RESET
CLKIN
and
and CLKIN (not including start-up time of external clock oscillator).
Figure
and
Figure
9.
CLKIN
8.
1
Figure 8. Clock Input
Figure 9. Reset
2
t
CKH
–18–
t
WRST
t
t
CK
CKL
Min
4t
8
CK
t
SRST
Min
20
7.5
7.5
10
Max
100 MHz
Max
80
40
40
3
30
Unit
ns
ns
ns
ns
ns
ns
ns
REV. 0
Unit