ADSP-21160NCB-100 Analog Devices Inc, ADSP-21160NCB-100 Datasheet - Page 2

• Manufacturer Part Number: ADSP-21160NCB-100
• Description: IC,DSP,32-BIT,CMOS,BGA,400PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21160NCB-100

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 100MHz
• Non-volatile Memory: External
• On-chip Ram: 512kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.90V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Package: 400BGA
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 100 MHz
• Ram Size: 512 KB
• Device Million Instructions Per Second: 100 MIPS

ADSP-21160N
KEY FEATURES (continued)
IEEE 1149.1 JTAG Standard Test Access Port and On-Chip
400-Ball 27 mm
200 Million Fixed-Point MACs Sustained Performance
Single Instruction Multiple Data (SIMD)
Parallelism in Buses and Computational Units Allows:
4M Bits On-Chip Dual-Ported SRAM for Independent
DMA Controller Supports:
Emulation
Architecture Provides:
Two Computational Processing Elements
Concurrent Execution—Each Processing Element
Code Compatibility—at Assembly Level, Uses the
Single-Cycle Execution (with or without SIMD) of: A
Transfers Between Memory and Core at up to Four
Accelerated FFT Butterfly Computation Through a
Access by Core Processor, Host, and DMA
14 Zero-Overhead DMA Channels for Transfers Between
Executes the Same Instruction, but Operates on
Different Data
Same Instruction Set as the ADSP-2106x
SHARC DSPs
Multiply Operation, An ALU Operation, A Dual
Memory Read or Write, and An Instruction Fetch
32-Bit Floating- or Fixed-Point Words per Cycle
Multiply with Add and Subtract
ADSP-21160N Internal Memory and External Memory,
External Peripherals, Host Processor, Serial Ports, or
Link Ports
27 mm Metric PBGA Package
–2–
4G Word Address Range for Off-Chip Memory
Memory Interface Supports Programmable Wait State
Multiprocessing Support Provides:
Serial Ports Provide:
64-Bit Background DMA Transfers at Core Clock Speed,
Host Processor Interface to 16- and 32-Bit
Generation and Page-Mode for Off-Chip Memory
Glueless Connection for Scalable DSP Multiprocessing
Distributed On-Chip Bus Arbitration for Parallel Bus
Six Link Ports for Point-to-Point Connectivity and Array
Two 50M Bits/s Synchronous Serial Ports with
Independent Transmit and Receive Functions
TDM Support for T1 and E1 Interfaces
64-Bit Wide Synchronous External Port Provides:
Glueless Connection to Asynchronous and SBSRAM
Up to 50 MHz Operation
in Parallel with Full-Speed Processor Execution
Microprocessors
Architecture
Connect of up to Six ADSP-21160Ns Plus Host
Multiprocessing
Companding Hardware
External Memories
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