ADSP-21160NCB-100 Analog Devices Inc, ADSP-21160NCB-100 Datasheet - Page 22

• Manufacturer Part Number: ADSP-21160NCB-100
• Description: IC,DSP,32-BIT,CMOS,BGA,400PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21160NCB-100

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 100MHz
• Non-volatile Memory: External
• On-chip Ram: 512kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.90V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Package: 400BGA
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 100 MHz
• Ram Size: 512 KB
• Device Million Instructions Per Second: 100 MIPS

ADSP-21160N
Memory Write—Bus Master
See
chronous interfacing to memories (and memory-mapped
peripherals) without reference to CLKIN. These specifications
Table 11. Memory Write—Bus Master
1
2
3
Parameter
Timing Requirements
t
t
t
t
Switching Characteristics
t
t
t
t
t
t
t
t
t
t
W = (number of wait states specified in WAIT register) × t
H = t
HI = t
I = t
ACK Delay/Setup: User must meet t
The falling edge of MSx, BMS is referenced.
See Example System Hold Time Calculation
DAAK
DSAK
SAKC
HAKC
DAWH
DAWL
WW
DDWH
DWHA
DWHD
DATRWH
WWR
DDWR
WDE
Table 11
MSx, BMS,
CK
ADDRESS
CK
CK
DMAGx
CLKIN
(if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).
DATA
WRx
RDx
ACK
(if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).
(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
CIF
and
Figure
ACK Delay from Address, Selects
ACK Delay from WRx Low
ACK Setup to CLKIN
ACK Hold After CLKIN
Address, CIF, Selects to WRx
Deasserted
Address, CIF, Selects to WRx Low
WRx Pulsewidth
Data Setup before WRx High
Address Hold after WRx Deasserted
Data Hold after WRx Deasserted
Data Disable after WRx Deasserted
WRx High to WRx, RDx, DMAGx Low 0.5t
Data Disable before WRx or RDx Low
WRx Low to Data Enabled
14. Use these specifications for asyn-
2
DAAK
t
DAW L
t
t
WD E
DAA K
or t
DSAK
on Page 41
or t
1
Figure 14. Memory Write—Bus Master
t
1
SAKC
D S AK
1
for calculation of hold times given capacitive and dc loads.
for deassertion of ACK (Low), all three specifications must be met for assertion of ACK (High).
1, 2
2
3
t
D AW H
–22–
t
SA KC
CK
Min
0.5t
1
t
0.25t
t
t
0.25t
0.25t
0.25t
0.25t
–0.25t
CK
CK
CK
.
t
apply when the ADSP-21160N is the bus master accessing
external memory space in asynchronous access mode. Note that
timing for ACK, DATA, RDx, WRx, and DMAGx strobe timing
parameters only applies to asynchronous access mode.
W W
– 0.25t
– 0.5t
– 0.5t
CCLK
CCLK
t
CCLK
CCLK
CCLK
CCLK
CCLK
DD WH
CCLK
+3
– 1+HI
CCLK
CCLK
– 3
– 1+H
– 1+H
– 2+H
– 1+I
CCLK
– 1
– 1+W
– 1+W
– 3+W
t
HA KC
Max
t
t
0.25t
CK
CK
– 0.75t
– 0.5t
CCLK
t
DAT RWH
CCLK
+2+H
CCLK
t
D WH D
–12+W
– 11+W
t
t
t
W W R
DD W R
DWHA
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
REV. 0
Unit