ADSP-21160NCB-100 Analog Devices Inc, ADSP-21160NCB-100 Datasheet - Page 8

• Manufacturer Part Number: ADSP-21160NCB-100
• Description: IC,DSP,32-BIT,CMOS,BGA,400PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21160NCB-100

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 100MHz
• Non-volatile Memory: External
• On-chip Ram: 512kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.90V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Package: 400BGA
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 100 MHz
• Ram Size: 512 KB
• Device Million Instructions Per Second: 100 MIPS

CROSSCORE is a trademark of Analog Devices, Inc.
VisualDSP++ is a registered trademark of Analog Devices, Inc.
ADSP-21160N
Link Ports
The ADSP-21160N features six 8-bit link ports that provide
additional I/O capabilities. With the capability of running at
100 MHz rates, each link port can support 80M bytes/s. Link
port I/O is especially useful for point-to-point interprocessor
communication in multiprocessing systems. The link ports can
operate independently and simultaneously. Link port data is
packed into 48- or 32-bit words, and can be directly read by the
core processor or DMA-transferred to on-chip memory. Each
link port has its own double-buffered input and output registers.
Clock/acknowledge handshaking controls link port transfers.
Transfers are programmable as either transmit or receive.
Serial Ports
The ADSP-21160N features two synchronous serial ports that
provide an inexpensive interface to a wide variety of digital and
mixed-signal peripheral devices. The serial ports can operate up
to half the clock rate of the core, providing each with a maximum
data rate of 50M bit/s. Independent transmit and receive
functions provide greater flexibility for serial communications.
Serial port data can be automatically transferred to and from on-
chip memory via a dedicated DMA. Each of the serial ports offers
a TDM multichannel mode. The serial ports can operate with
little-endian or big-endian transmission formats, with word
lengths selectable from 3 bits to 32 bits. They offer selectable
synchronization and transmit modes as well as optional µ-law or
A-law companding. Serial port clocks and frame syncs can be
internally or externally generated.
Host Processor Interface
The ADSP-21160N host interface allows easy connection to
standard microprocessor buses, both 16-bit and 32-bit, with little
additional hardware required. The host interface is accessed
through the ADSP-21160N’s external port and is memory-
mapped into the unified address space. Four channels of DMA
are available for the host interface; code and data transfers are
accomplished with low software overhead. The host processor
communicates with the ADSP-21160N’s external bus with host
bus request (HBR), host bus grant (HBG), ready (REDY),
acknowledge (ACK), and chip select (CS) signals. The host can
directly read and write the internal memory of the ADSP-
21160N, and can access the DMA channel setup and mailbox
registers. Vector interrupt support provides efficient execution of
host commands.
Program Booting
The internal memory of the ADSP-21160N can be booted at
system power-up from an 8-bit EPROM, a host processor, or
through one of the link ports. Selection of the boot source is
controlled by the BMS (Boot Memory Select), EBOOT
(EPROM Boot), and LBOOT (Link/Host Boot) pins. 32-bit and
16-bit host processors can be used for booting.
Phase-Locked Loop
The ADSP-21160N uses an on-chip PLL to generate the internal
clock for the core. Ratios of 2:1, 3:1, and 4:1 between the core
and CLKIN are supported. The CLK_CFG pins are used to
select the ratio. The CLKIN rate is the rate at which the synchro-
nous external port operates.
–8–
Power Supplies
The ADSP-21160N has separate power supply connections for
the internal (V
AGND) power supplies. The internal and analog supplies must
meet the 1.9 V requirement. The external supply must meet the
3.3 V requirement. All external supply pins must be connected
to the same supply.
The PLL Filter,
21160N in the system. V
recommended that the capacitors be connected directly to
AGND using short thick trace. It is recommended that the capac-
itors be placed as close to AV
connection from AGND to the (digital) ground plane should be
made after the capacitors. The use of a thick trace for AGND is
reasonable only because the PLL is a relatively low power
circuit—it does not apply to any other ADSP-21160N GND
connection.
Development Tools
The ADSP-21160N is supported with a complete set of
CROSSCORE™ software and hardware development tools,
including Analog Devices emulators and VisualDSP++
opment environment. The same emulator hardware that
supports other ADSP-2116x processors also fully emulates the
ADSP-21160N.
The VisualDSP++ project management environment lets pro-
grammers develop and debug an application. This environment
includes an easy to use assembler (which is based on an algebraic
syntax), an archiver (librarian/library builder), a linker, a loader,
a cycle-accurate instruction-level simulator, a C/C++ compiler,
and a C/C++ runtime library that includes DSP and mathemat-
ical functions. A key point for these tools is C/C++ code
efficiency. The compiler has been developed for efficient transla-
tion of C/C++ code to DSP assembly. The DSP has architectural
features that improve the efficiency of compiled C/C++ code.
The VisualDSP++ debugger has a number of important features.
Data visualization is enhanced by a plotting package that offers
a significant level of flexibility. This graphical representation of
user data enables the programmer to quickly determine the per-
formance of an algorithm. As algorithms grow in complexity, this
capability can have increasing significance on the designer’s
development schedule, increasing productivity. Statistical
profiling enables the programmer to nonintrusively poll the
processor as it is running the program. This feature, unique to
VisualDSP++, enables the software developer to passively gather
important code execution metrics without interrupting the real-
time characteristics of the program. Essentially, the developer can
identify bottlenecks in software quickly and efficiently. By using
the profiler, the programmer can focus on those areas in the
program that impact performance and take corrective action.
V
Figure 5. Analog Power (AV
DDINT
DDINT
Figure
), external (V
10
5, must be added for each ADSP-
DDINT
0.1 F
DD
is the digital core supply. It is
AGND
and AGND as possible. The
DDEXT
), and analog (AV
DD
0.01 F
) Filter Circuit
AV
DD
®
DD
REV. 0
devel-
and