ADSP-21160NCB-100 Analog Devices Inc, ADSP-21160NCB-100 Datasheet - Page 32

• Manufacturer Part Number: ADSP-21160NCB-100
• Description: IC,DSP,32-BIT,CMOS,BGA,400PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21160NCB-100

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 100MHz
• Non-volatile Memory: External
• On-chip Ram: 512kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.90V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Package: 400BGA
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 100 MHz
• Ram Size: 512 KB
• Device Million Instructions Per Second: 100 MIPS

ADSP-21160N
DMA Handshake
See
three DMA handshake modes. In all three modes, DMARx is
used to initiate transfers. For handshake mode, DMAGx controls
the latching or enabling of data externally. For external hand-
shake mode, the data transfer is controlled by the ADDR31–0,
RDx, WRx, PAGE, MS3–0, ACK, and DMAGx signals. For
Table 18. DMA Handshake
1
2
3
4
5
6
7
Parameter
Timing Requirements
t
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
W = (number of wait states specified in WAIT register)
HI = t
Only required for recognition in the current cycle.
Maximum throughput using DMARx/DMAGx handshaking equals t
t
Use t
t
See Example System Hold Time Calculation
This parameter applies for synchronous access mode only.
SDRC
WDR
SDATDGL
HDATIDG
DATDRH
DMARLL
DMARH
DDGL
WDGH
WDGL
HDGC
VDATDGH
DATRDGH
DGWRL
DGWRH
DGWRR
DGRDL
DRDGH
DGRDR
DGWR
DADGH
DDGHA
limit applies to non-synchronous access mode only.
SDATDGL
the write, the data can be driven t
VDATDGH
t
VDATDGH
Table 18
DMARLL
CK
is the data setup requirement if DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of
is valid if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then
(if data bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
= t
if DMARx transitions synchronous with CLKIN. Otherwise, use t
CK
and
– .25t
Figure
DMARx Setup Before CLKIN
DMARx Width Low (Nonsynchronous)
Data Setup After DMAGx Low
Data Hold After DMAGx High
Data Valid After DMARx High
DMARx Low Edge to Low Edge
DMARx Width High
DMAGx Low Delay After CLKIN
DMAGx High Width
DMAGx Low Width
DMAGx High Delay After CLKIN
Data Valid Before DMAGx High
Data Disable After DMAGx High
WRx Low Before DMAGx Low
DMAGx Low Before WRx High
WRx High Before DMAGx High
RDx Low Before DMAGx Low
RDx Low Before DMAGx High
RDx High Before DMAGx High
DMAGx High to WRx, RDx, DMAGx
Low
Address/Select Valid to DMAGx High
Address/Select Hold after DMAGx High
CCLK
21. These specifications describe the
– 8 + (n × t
DATDRH
CK
after DMARx is brought high.
) where n equals the number of extra cycles that the access is prolonged.
on Page 41
2
for calculation of hold times given capacitive and dc loads.
1
3
3
4
7
5
7
6
WDR
+ t
–32–
2
t
CK
DMARH
.
Min
3
0.5t
2
t
0.5t
0.25t
0.5t
t
t
t
0.25t
–1.5
t
–1.5
–1.5
t
–1.5
0.5t
15.5
1
Paced Master mode, the data transfer is controlled by
ADDR31–0, RDx, WRx, MS3–0, and ACK (not DMAG). For
Paced Master mode, the Memory Read-Bus Master, Memory
Write-Bus Master, and Synchronous Read/Write-Bus Master
timing specifications for ADDR31–0, RDx, WRx, MS3–0,
PAGE, DATA63–0, and ACK also apply.
CK
CK
CK
CK
CK
CK
WDR
= (0.5t
– 0.5t
– 0.25t
– 0.25t
– 0.5t
– 0.5t
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
and t
+2.5
+1
– 1+HI
– 2+HI
CCLK
CCLK
CCLK
CCLK
+1
DMARH
– 3
CCLK
CCLK
+1) + (0.5t
–2+W
– 1
– 2 +W
+1.5
– 8
.
CCLK
+1)=10.0 ns (100 MHz). This throughput
Max
t
t
0.25t
t
t
0.25t
2
2
2
2
CK
CK
CK
CK
+3
– 0.5t
– 0.25t
– 0.25t
CCLK
CCLK
CCLK
+9
+1.5
CCLK
CCLK
–7
+9
+5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
REV. 0
Unit