ADSP-21160NCB-100 Analog Devices Inc, ADSP-21160NCB-100 Datasheet - Page 36

• Manufacturer Part Number: ADSP-21160NCB-100
• Description: IC,DSP,32-BIT,CMOS,BGA,400PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21160NCB-100

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 100MHz
• Non-volatile Memory: External
• On-chip Ram: 512kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.90V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Package: 400BGA
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 100 MHz
• Ram Size: 512 KB
• Device Million Instructions Per Second: 100 MIPS

ADSP-21160N
Serial Ports
For Serial Ports, see
Table
determine whether communication is possible between two
Table 21. Serial Ports—External Clock
1
Table 22. Serial Ports—Internal Clock
1
Table 23. Serial Ports—External or Internal Clock
1
Table 24. Serial Ports—External Clock
1
Table 25. Serial Ports—Enable and Three-State
1
Parameter
Timing Requirements
t
t
t
t
t
t
Parameter
Timing Requirements
t
t
t
t
Parameter
Switching Characteristics
t
t
Parameter
Switching Characteristics
t
t
t
t
Parameter
Switching Characteristics
t
t
t
t
Referenced to sample edge.
Referenced to sample edge.
Referenced to drive edge.
Referenced to drive edge.
Referenced to drive edge.
SFSE
HFSE
SDRE
HDRE
SCLKW
SCLK
SFSI
HFSI
SDRI
HDRI
DFSE
HOFSE
DFSE
HOFSE
DDTE
HDTE
DDTEN
DDTTE
DDTIN
DDTTI
25,
Table
26,
TFS/RFS Setup Before TCLK/RCLK
TFS/RFS Hold After TCLK/RCLK
Receive Data Setup Before RCLK
Receive Data Hold After RCLK
TCLK/RCLK Width
TCLK/RCLK Period
TFS Setup Before TCLK
TFS/RFS Hold After TCLK/RCLK
Receive Data Setup Before RCLK
Receive Data Hold After RCLK
RFS Delay After RCLK (Internally Generated RFS)
RFS Hold After RCLK (Internally Generated RFS)
TFS Delay After TCLK (Internally Generated TFS)
TFS Hold After TCLK (Internally Generated TFS)
Transmit Data Delay After TCLK
Transmit Data Hold After TCLK
Data Enable from External TCLK
Data Disable from External TCLK
Data Enable from Internal TCLK
Data Disable from Internal TCLK
Table
Table
21,
27,
Table
Figure
22,
24, and
Table
Figure
1
23,
; RFS Setup Before RCLK
Table
25. To
1
1
1
1
1
1
1
1
1
1
24,
1
1
1
–36–
devices at clock speed n, the following specifications must be
confirmed: 1) frame sync delay and frame sync setup and hold,
2) data delay and data setup and hold, and 3) SCLK width.
1
1
1
1
1
Min
3.5
4
1.5
6.5
8
2t
Min
8
t
6.5
3
Min
3
Min
3
0
Min
4
0
CCLK
CCLK
/2 + 1
Max
Max
13
Max
13
16
Max
10
3
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
REV. 0
Unit
ns
Unit
Unit
Unit