ADSP-21160NCB-100 Analog Devices Inc, ADSP-21160NCB-100 Datasheet - Page 40

• Manufacturer Part Number: ADSP-21160NCB-100
• Description: IC,DSP,32-BIT,CMOS,BGA,400PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21160NCB-100

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 100MHz
• Non-volatile Memory: External
• On-chip Ram: 512kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.90V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Package: 400BGA
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 100 MHz
• Ram Size: 512 KB
• Device Million Instructions Per Second: 100 MIPS

ADSP-21160N
Output Drive Currents
Figure 27
of the ADSP-21160N. The curves represent the current drive
capability of the output drivers as a function of output voltage.
Power Dissipation
Total power dissipation has two components, one due to internal
circuitry and one due to the switching of external output drivers.
Internal power dissipation is dependent on the instruction
execution sequence and the data operands involved. Using the
current specifications (I
from Electrical Characteristics
versus-operation information in
estimate the ADSP-21160N’s internal power supply (V
input current for a specific application, according to the formula.
Table 29. ADSP-21160N Operation Types vs. Input Current
1
2
Operation
Instruction Type
Instruction Fetch
Core Memory Access
Internal Memory DMA
External Memory DMA
Data Bit Pattern for Core
Memory Access and DMA
Peak Activity=I
These assume a 2:1 core clock ratio. For more information on ratios and clocks (t
influence these calculations.
–20
–40
–60
–80
80
60
40
20
0
0
shows typical I–V characteristics for the output drivers
V
DDEXT
Figure 27. Typical Drive Currents
DD-INPEAK
0.5
V
= 3.11V, 115°C
DDEXT
V
OL
V
SWEEP (V
DDEXT
= 3.47V, –45°C
1
, High Activity=I
DD-INPEAK
2
= 3.3V, 25°C
1.5
V
DDEXT
DDEXT
on Page 14
, I
Table
V
DDEXT
) VOLTAGE – V
Peak Activity
Multifunction
Cache
2 per t
(DM
1 per 2 t
1 per External Port Cycle ( 64) 1 per External Port Cycle (
Worst Case
DD-INHIGH
= 3.11V, 115°C
2
= 3.47V, –45°C
DD-INHIGH
V
29, engineers can
OH
CK
V
, I
DDEXT
2.5
64 and PM
and the current-
CCLK
Cycle
DD-INLOW
, and Low Activity=I
= 3.3V, 25°C
Cycles
1
3
, I
DD-IDLE
3.5
DDINT
64)
)
)
–40–
DD-INLOW
The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:
and is calculated by:
The load capacitance should include the processor’s package
capacitance (C
load high and then back low. Address and data pins can drive high
and low at a maximum rate of 1/(2t
switch every cycle at a frequency of 1/t
1/(2t
Example: Estimate P
The P
can drive, as shown in
conditions by adding a typical internal power dissipation:
A typical power consumption can now be calculated for these
High Activity
Multifunction
Internal Memory
1 per t
1 per 2 t
Random
the number of output pins that switch during each
cycle (O)
the maximum frequency at which they can switch (f)
their load capacitance (C)
their voltage swing (V
A system with one bank of external data memory—asyn-
chronous RAM (64-bit)
Four 64K × 16 RAM chips are used, each with a load
of 10 pF
External data memory writes occur every other cycle, a
rate of 1/(2 t
The bus cycle time is 50 MHz (t
(DM
CK
CK
. The state of the PEYEN bit (SIMD versus SISD mode) does not
and t
EXT
), but selects can switch on each cycle.
CK
equation is calculated for each class of pins that
CCLK
CCLK
64)
Cycle
), see the timing ratio definitions
IN
P
CK
Cycles
). The switching frequency includes driving the
1
TOTAL
), with 50% of the pins switching
P
% High I
% Peak I
EXT
% Low I
+ % Idle I
---------------------------------------------------- -
EXT
Table
= P
= O × C × V
with the following assumptions:
DD
EXT
I
)
DDINT
30.
+ P
DD-INPEAK
DD-INHIGH
DD-INLOW
DD-IDLE
64) None
INT
CK
). The write strobe can
CK
+ P
DD
CK
Low Activity
Single Function
Internal Memory
None
None
N/A
2
. Select pins switch at
= 20 ns).
PLL
× f
on Page
16.
1
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