ADSP-21160NCB-100 Analog Devices Inc, ADSP-21160NCB-100 Datasheet - Page 5

• Manufacturer Part Number: ADSP-21160NCB-100
• Description: IC,DSP,32-BIT,CMOS,BGA,400PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21160NCB-100

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 100MHz
• Non-volatile Memory: External
• On-chip Ram: 512kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.90V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Package: 400BGA
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 100 MHz
• Ram Size: 512 KB
• Device Million Instructions Per Second: 100 MIPS

SIMD Computational Engine
The ADSP-21160N contains two computational processing
elements that operate as a Single Instruction Multiple Data
(SIMD) engine. The processing elements are referred to as PEX
and PEY, and each contains an ALU, multiplier, shifter, and
register file. PEX is always active, and PEY may be enabled by
setting the PEYEN mode bit in the MODE1 register. When this
mode is enabled, the same instruction is executed in both pro-
cessing elements, but each processing element operates on
different data. This architecture is efficient at executing math-
intensive DSP algorithms.
Entering SIMD mode also has an effect on the way data is trans-
ferred between memory and the processing elements. When in
SIMD mode, twice the data bandwidth is required to sustain
computational operation in the processing elements. Because of
this requirement, entering SIMD mode also doubles the
bandwidth between memory and the processing elements. When
using the DAGs to transfer data in SIMD mode, two data values
are transferred with each access of memory or the register file.
Independent, Parallel Computation Units
Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier, and shifter. These units perform single-cycle
instructions. The three units within each processing element are
arranged in parallel, maximizing computational throughput.
Single multifunction instructions execute parallel ALU and mul-
tiplier operations. In SIMD mode, the parallel ALU and
multiplier operations occur in both processing elements. These
computation units support IEEE 32-bit single-precision floating-
point, 40-bit extended precision floating-point, and 32-bit fixed-
point data formats.
Data Register File
A general-purpose data register file is contained in each process-
ing element. The register files transfer data between the
computation units and the data buses, and store intermediate
results. These 10-port, 32-register (16 primary, 16 secondary)
register files, combined with the ADSP-2116x enhanced Harvard
architecture, allow unconstrained data flow between computa-
tion units and internal memory. The registers in PEX are referred
to as R0–R15 and in PEY as S0–S15.
Single-Cycle Fetch of Instruction and Four Operands
The ADSP-21160N features an enhanced Harvard architecture
in which the data memory (DM) bus transfers data, and the
program memory (PM) bus transfers both instructions and data
(see the functional block diagram
21160N’s separate program and data memory buses and on-chip
instruction cache, the processor can simultaneously fetch four
operands and an instruction (from the cache), all in a single cycle.
Instruction Cache
The ADSP-21160N includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and four
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This cache
REV. 0
on Page
1). With the ADSP-
–5–
allows full-speed execution of core, providing looped operations,
such as digital filter multiply- accumulates and FFT butterfly
processing.
Data Address Generators with Hardware
Circular Buffers
The ADSP-21160N’s two data address generators (DAGs) are
used for indirect addressing and provide for implementing
circular data buffers in hardware. Circular buffers allow efficient
programming of delay lines and other data structures required in
digital signal processing, and are commonly used in digital filters
and Fourier transforms. The two DAGs of the ADSP-21160N
contain sufficient registers to allow the creation of up to 32
circular buffers (16 primary register sets, 16 secondary). The
DAGs automatically handle address pointer wraparound,
reducing overhead, increasing performance, and simplifying
implementation. Circular buffers can start and end at any
memory location.
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of parallel
operations, for concise programming. For example, the ADSP-
21160N can conditionally execute a multiply, an add, and
subtract, in both processing elements, while branching, all in a
single instruction.
ADSP-21160N Memory and I/O Interface Features
Augmenting the ADSP-2116x family core, the ADSP-21160N
adds the following architectural features:
Dual-Ported On-Chip Memory
The ADSP-21160N contains four megabits of on-chip SRAM,
organized as two blocks of 2M bits each, which can be configured
for different combinations of code and data storage. Each
memory block is dual-ported for single-cycle, independent
accesses by the core processor and I/O processor. The dual-
ported memory in combination with three separate on-chip buses
allows two data transfers from the core and one from I/O proces-
sor, in a single cycle. On the ADSP-21160N, the memory can be
configured as a maximum of 128K words of 32-bit data, 256K
words of 16-bit data, 85K words of 48-bit instructions (or 40-bit
data), or combinations of different word sizes up to four megabits.
All of the memory can be accessed as 16-bit, 32-bit, 48-bit, or
64-bit words. A 16-bit floating-point storage format is supported
that effectively doubles the amount of data that may be stored
on-chip. Conversion between the 32-bit floating-point and 16-
bit floating-point formats is done in a single instruction. While
each memory block can store combinations of code and data,
accesses are most efficient when one block stores data, using the
DM bus for transfers, and the other block stores instructions and
data, using the PM bus for transfers. Using the DM bus and PM
bus in this way, with one dedicated to each memory block, assures
single-cycle execution with two data transfers. In this case, the
instruction must be available in the cache.
Off-Chip Memory and Peripherals Interface
The ADSP-21160N’s external port provides the processor’s
interface to off-chip memory and peripherals. The 4G word off-
chip address space is included in the ADSP-21160N’s unified
address space. The separate on-chip buses—for PM addresses,
ADSP-21160N