ADSP-21160NCB-100 Analog Devices Inc, ADSP-21160NCB-100 Datasheet - Page 21

• Manufacturer Part Number: ADSP-21160NCB-100
• Description: IC,DSP,32-BIT,CMOS,BGA,400PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21160NCB-100

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 100MHz
• Non-volatile Memory: External
• On-chip Ram: 512kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.90V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Package: 400BGA
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 100 MHz
• Ram Size: 512 KB
• Device Million Instructions Per Second: 100 MIPS

Memory Read—Bus Master
See
chronous interfacing to memories (and memory-mapped
peripherals) without reference to CLKIN. These specifications
Table 10. Memory Read—Bus Master
1
2
3
4
REV. 0
Parameter
Timing Requirements
t
t
t
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
W = (number of wait states specified in WAIT register)
HI = t
H = t
Data Delay/Setup: User must meet t
The falling edge of MSx, BMS is referenced.
Data Hold: User must meet t
ACK Delay/Setup: User must meet t
DAD
DRLD
HDA
SDS
HDRH
DAAK
DSAK
SAKC
HAKC
DRHA
DARL
RW
RWR
hold times given capacitive and dc loads.
Table 10
CK
CK
(if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).
(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
and
ADDRESS
MSx, CIF
DMAGx
CLKIN
DATA
WRx
Figure
BMS
ACK
RDx
Address, CIF, Selects Delay to Data Valid
RDx Low to Data Valid
Data Hold from Address, Selects
Data Setup to RDx High
Data Hold from RDx High
ACK Delay from Address, Selects
ACK Delay from RDx Low
ACK Setup to CLKIN
ACK Hold After CLKIN
Address, CIF, Selects Hold After RDx High 0.25t
Address, CIF, Selects to RDx Low
RDx Pulsewidth
RDx High to WRx, RDx, DMAGx Low
13. Use these specifications for asyn-
HDA
or t
DAAK
DAD
HDRH
, t
, t
DRLD
t
DSAK
in asynchronous access mode. See Example System Hold Time Calculation
DARL
t
DAAK
, or t
, or t
4
Figure 13. Memory Read—Bus Master
1
SDS
SAKC
1
.
3
4
for deassertion of ACK (Low), all three specifications must be met for assertion of ACK (High).
t
DSAK
t
DAD
3
2, 4
2
t
DRLD
–21–
1, 2
t
CK
t
SAKC
.
apply when the ADSP-21160N is the bus master accessing
external memory space in asynchronous access mode. Note that
timing for ACK, DATA, RDx, WRx, and DMAGx strobe timing
parameters only applies to asynchronous access mode.
0
8
1
0.5t
0.25t
t
0.5t
Min
1
CK
t
RW
– 0.5t
CCLK
CCLK
CCLK
CCLK
+3
– 1+HI
CCLK
– 3
– 1+H
– 1+W
t
SDS
t
HAKC
Max
t
t
t
t
CK
CK
CK
CK
– 0.25t
– 0.5t
– 0.5t
– 0.75t
ADSP-21160N
on Page 41
t
HDRH
CCLK
CCLK
t
HDA
CCLK
CCLK
t
t
DRHA
RWR
– 12+W
+W
– 11+W
– 11+W
for the calculation of
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns