ADSP-21160NCB-100 Analog Devices Inc, ADSP-21160NCB-100 Datasheet - Page 6

• Manufacturer Part Number: ADSP-21160NCB-100
• Description: IC,DSP,32-BIT,CMOS,BGA,400PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21160NCB-100

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 100MHz
• Non-volatile Memory: External
• On-chip Ram: 512kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.90V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Package: 400BGA
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 100 MHz
• Ram Size: 512 KB
• Device Million Instructions Per Second: 100 MIPS

ADSP-21160N
PM data, DM addresses, DM data, I/O addresses, and I/O data—
are multiplexed at the external port to create an external system
bus with a single 32-bit address bus and a single 64-bit data bus.
The lower 32 bits of the external data bus connect to even
addresses and the upper 32 bits of the 64 connect to odd
addresses. Every access to external memory is based on an
address that fetches a 32-bit word, and with the 64-bit bus, two
address locations can be accessed at once. When fetching an
instruction from external memory, two 32-bit data locations are
being accessed (16 bits are unused).
alignment of various accesses to external memory.
The external port supports asynchronous, synchronous, and syn-
chronous burst accesses. ZBT synchronous burst SRAM can be
interfaced gluelessly. Addressing of external memory devices is
facilitated by on-chip decoding of high order address lines to
generate memory bank select signals. Separate control lines are
also generated for simplified addressing of page-mode DRAM.
The ADSP-21160N provides programmable memory wait states
and external memory acknowledge controls to allow interfacing
to DRAM and peripherals with variable access, hold, and disable
time requirements.
Multiprocessor
Memory
Space
Internal
Memory
Space
Normal Word
Short Word
Long Word
Broadcast
IOP Reg’s
(ID = 001)
(ID = 010)
(ID = 011)
(ID = 100)
(ID = 101)
(ID = 110)
(ID = 111)
All DSPs
Memory
Memory
Memory
Memory
Memory
Memory
Write to
Internal
Internal
Internal
Internal
Internal
Internal
Space
Space
Space
Space
Space
Space
Figure 2. Memory Map
0x40 0000
0x00 0000
0x02 0000
0x04 0000
0x08 0000
0x10 0000
0x20 0000
0x30 0000
0x50 0000
0x60 0000
0x70 0000
0x7F FFFF
Figure 3
Nonbanked
Bank 0
Bank 1
Bank 2
Bank 3
shows the
0x80 0000
0xFFFF FFFF
External
Memory
Space
MS
MS
MS
MS
0
1
2
3
–6–
DMA Controller
The ADSP-21160N’s on-chip DMA controller allows zero-
overhead data transfers without processor intervention. The
DMA controller operates independently and invisibly to the
processor core, allowing DMA operations to occur while the core
is simultaneously executing its program instructions. DMA
transfers can occur between the ADSP-21160N’s internal
memory and external memory, external peripherals, or a host
processor. DMA transfers can also occur between the ADSP-
21160N’s internal memory and its serial ports or link ports.
External bus packing to 16-, 32-, 48-, or 64-bit words is
performed during DMA transfers. Fourteen channels of DMA
are available on the ADSP-21160N—six via the link ports, four
via the serial ports, and four via the processor’s external port (for
either host processor, other ADSP-21160Ns, memory or I/O
transfers). Programs can be downloaded to the ADSP-21160N
using DMA transfers. Asynchronous off-chip peripherals can
control two DMA channels using DMA Request/Grant lines
(DMAR1–2, DMAG1–2). Other DMA features include
interrupt generation upon completion of DMA transfers, two-
dimensional DMA, and DMA chaining for automatic linked
DMA transfers.
Multiprocessing
The ADSP-21160N offers powerful features tailored to multi-
processing DSP systems as shown in
and link ports provide integrated glueless multiprocessing
support.
The external port supports a unified address space (see
that allows direct interprocessor accesses of each ADSP-
21160N’s internal memory. Distributed bus arbitration logic is
included on-chip for simple, glueless connection of systems con-
taining up to six ADSP-21160Ns and a host processor. Master
processor changeover incurs only one cycle of overhead. Bus
arbitration is selectable as either fixed or rotating priority. Bus
lock allows indivisible read-modify-write sequences for sema-
phores. A vector interrupt is provided for interprocessor
63
64-BIT TRANSFER FOR 48-BIT INSTRUCTION FETCH
32-BIT NORMAL WORD (ODD ADDRESS)
64-BIT TRANSFER FOR 40-BIT EXTENDED PRECISION
BYTE 7
64-BIT LONG WORD, SIMD, DMA, IOP REGISTER TRANSFERS
Figure 3. External Data Alignment Options
55
RESTRICTED DMA, HOST, EPROM DATA ALIGNMENTS:
32-BIT PACKED
RDH/WRH
47
16-BIT PACKED
39
EPROM
32-BIT NORMAL WORD (EVEN ADDRESS)
DATA63–0
31
Figure
23
RDL/WRL
4. The external port
15
7
BYTE 0
Figure
REV. 0
0
2)